ADS8688AEVM-PDK: About operation of EVM

Hi Tom,

(1) ADS8688/84 integrates an analog front-end (AFE,PGA) on every channel, there is an internal bias voltage signal (~2.2V) provided to this AFE as shown in below picture 1, the input signal is biased to the appropriate common-mode voltage level for proper operation of internal ADC core. When there is an available input signal on ADC input, the available signal will dominate it, if the input is floating and no any signal, the bias voltage will be observed, the converted voltage/code may be different for different front-end RC filter if a pull down resistor is used before filter. Since these ADCs support true bipolar input signals using a single +5V power supply, the internal biasing cannot be done to provide a zero offset at ADC output when the inputs are left floating.

One of the advantages of this input stage is that it offers a 1-MOhm constant resistive input impedance.  This makes the inputs relatively easy to drive (in most cases) without additional driver amplifiers or buffers. General switched-capacitor input structure ADC needs a lot of cautions to design front-end amplifier and RC filter, any improper amplifier and RC selection will lead to large error to settle the signal on internal sampling capacitors and will get worse performance result, but the front-end design for these ADS8688/84 ADCs with such integrated AFE will be much easier, and the ADCs can be driven directly without any external amplifier because the AFE and ADC driver have been integrated into these ADCs.

Hence, this is not an issue and it was known when the ADCs were designed for this structure and these benefits, if checked the datasheet and measured on EVM board, this voltage could be observed in advance. This is very common for the ADCs with such integrated AFE and input structure.

(2) Can you please have a screenshot for this question?  thanks.

Best regards

Dale

Hi Dale,

Thank you for your answer.
For the question(2), my customer will send me the screenshot later.

For the question(1), he has an additional question blow.
As described at Table-1 in Page25 of datesheet of ADS8688A
"Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ"
If RS is less than 30 KΩ, is it no problem?
(If possible, it should be as close as possible to 0 Ω.)
The results indicated in Table 1 are also based on an assumption that an analog input pins are driven by very low impedance sources (RS is approximately 0).
I am designing with RS of 470 ohms.
Also, I put 0.1 uF in AIN_nP and AIN_nGND after RS ​​to reduce noise, but could you give me some advice if such a circuit seems to have problems.
(If you look at the circuit of the ADS8688AEVM-PDK document (page 39), RS = 357 Ω, 0.01 uF.)

Best regards,
Tom

Hi Tom,

I apologized for late response for some reasons.

You have a misunderstanding on the condition of "when the AVDD pin of the device is connected to the power supply voltage(AVDD=5V) or offers a low impedance of 30kohm" in the table 1 and section of 8.3.3(input overvoltage protection circuit)", this impedance refers to the impedance of power supply, not the input signal source. Basically, this is the condition when the AVDD is available (for table 1) or floating(no power supply for table 2).

There is no issue for your 470ohm input resistor on ADC's input, the difference of your resistor from 357ohm on the EVM board is the different cutoff frequency of filter if the capacitor is same.

Thanks&regards,

Dale