Other Parts Discussed in Thread: ADS8353
Hi Team,
In the slides of "Building the SAR ADC Simulation Model", what is the corresponding parameter for 10ns? Can we find related information in ADS8860 datasheet? Thank you.
Best Regards,
Hongjia
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Hi Hongjia,
As I introduced and talked to you guys at the Plabs ADC training , this 10ns timing is used to reset the charge on the internal sample-hold capacitor of ADC at the end of cycle through the reset switch, so every time the signal on the sample-hold capacitor can be settled from the worst 0V to the highest +5V on ADS8860 ADC. This is just for simulation purpose to check the settling error on the sample-hold capacitor as the worst case.
Best regards
Dale