ADC128S102QML-SP: Minimum Slew Rate for DI and SCLK

Steve Widener

Genius 11010 points

Part Number: ADC128S102QML-SP

What is the minimum slew rate for the DI and SCLK lines over temperature, process and radiation?

Can this be derived from the 0.8MHz operating speed and the DC limits in the electrical characteristics alone?

over 6 years ago

0 Kirby Kruckmeyer96848 over 6 years ago

TI__Genius 17125 points

Hi Steve,

I am not sure I understand the question or why "slew rate" would be a concern. What is important is to meet the timing requirements shown in section 6.8. Those limits are valid over temperature and radiation.

Kirby

0 Steve Widener over 6 years ago in reply to Kirby Kruckmeyer96848

TI__Genius 11010 points

Thanks Kirby - I'll figure out min rise time base don the duty cycle and 800kHz min operating.

In this application, I believe that the edges are being slowed to minimize EMI.

0 Kirby Kruckmeyer96848 over 6 years ago in reply to Steve Widener

TI__Genius 17125 points

Steve, if rise and fall time are a significant part of the clock cycle, then you should be evaluating the time requirements based on Vil and Vih and not the full SCLK voltage swing.

0 Steve Widener over 6 years ago in reply to Kirby Kruckmeyer96848

TI__Genius 11010 points

Agreed!

I calculated ~ 30V/usec. This is similar to other guidance I have for SCLK/SDI interface and have recommended not going any slower than that rate.

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ADC128S102QML-SP: Minimum Slew Rate for DI and SCLK