ADS5562: Data converters forum

Ken_7001

Prodigy 50 points

Part Number: ADS5562
Other Parts Discussed in Thread: ADS5560

Hi,

We have tested ADS5562 on our designed circuit board.

Then we encountered bizarre phenomenon as attached file (please refer it, which is pasted on excel file )

We observed the ADC output which appear big different data alternately.

(2c81h,2d34h,2c7eh,2d36h,2c8ah,2d3ah....... as row of the data)

And Odd or Even interval signal is no problem just like noise level ripple.

first of all, we inferred the mistake connection of bit alignment or the jitters of LVDS outputs.

But we found no mistake because output signal could trace input signal articulately.

Next, we also inferred the periodic analog input noise.

If so, I think that it changes more randomly with no regular manner.

It looks like that two ADC exist on the same chip and they are converting input data each other alternately.

Please let us know why such conversion happen.

Thank you and Best Regards,

Kenjiro

over 6 years ago

0 Yusuf%20Agoro over 6 years ago

TI__Expert 4880 points

Ken,

Can you please try re-sending the excel file. it seems the link is broken. Can you also re-state the issue you are seeing just so that i have a clear understanding. From what i can tell it seems that you are doubting whether the codes you are receiving from the ADC are valid? Have you tried taking an FFT of the data to see what frequency spectrum looks like? If so can you send that to me as well. Please help me better understand the issue you are seeing.

Yusuf

0 Ken_7001 over 6 years ago in reply to Yusuf%20Agoro

Prodigy 50 points

Hi Yusuf-san,

I attached PDF file again.

I adopted LTC6363(differential amp.) as input buffer of ADS5562 and Spartan-7 for data processing of ADS5562.

The DDR de-serialize IP is used to separate odd data and even data each other and combine them to 16bit data.

And the data is stored in the dual port memory, directly.

Then, I made the tap between DDR IP and the memory, and checked the signals by logic analyzer which is equipped in VIVADO IDE FPGA compiler.

I presume that these actions are no problem to get actual 16bit data.

Now, Input and output linearity as macro view is OK.

However, the data hopping between adjacent data as bizarre phenomenon, happen as noise level view.

Thank you and Best Regards,

Kenjiro

ADC_TEST.pdf

0 Ken_7001 over 6 years ago in reply to Yusuf%20Agoro

Prodigy 50 points

Yusuf-san,

This is second mail to you.

Does ADS5562 adopt interleave ADC method (two ADC equipped on the chip, and alternately be activated )?

Because 40MHz spurious (just Nyquist frequency) is generated when sampling frequency is 80MHz.

This frequency is not affect SN ratio.

If so, I presume that noise histogram makes two peak distribution shape, but the datasheet shows only one peak normal distribution shape.

I do not why.

If it takes interleave method, I can understand this phenomenon.

The last digit of 40MHz version of this ADC series is 0 (ADS5560), but 80MHz version is 2 (ADS5562). Doesn't the last digit implies the number of ADS ?

Thank you

Kenjiro

0 Yusuf%20Agoro over 6 years ago in reply to Ken_7001

TI__Expert 4880 points

Kenjiro,

To answer your question the device has a pipeline architecture without interleaving. The noise you see at 40 MHz is probably because low frequency noise correction is possibly enabled (see section 7.3.1 Low-Frequency Noise Suppression, page 26 of the datasheet). Then I have two suggestions for you to try.

1. Try experimenting with the low-frequency noise suppression feature by enabling the bit in the register shown in the image below.

2. Another suggestion would be to try and low frequency sine wave instead of a DC and see if the results are as expected.

Thanks

Yusuf