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ADC128S102QML-SP: ADC128S102QML-SP SCLK Duty-Cycle Limits

Michael Althaus
Prodigy 10 points
Part Number: ADC128S102QML-SP


The datasheet ((SNAS411P –AUGUST 2008–REVISED APRIL 2017) is not very clear about SCLK duty-cycle limits and low/high time requirements; only typical values are given (duty-cycle 40%..60% and SCLK low/high 0.4 times clock time).

  1. What are the absolute limits for SCLK duty-cycle and low/high times for which the device is still guaranteed to operate?
  2. It is likely that duty-cycles outside the typical range have an impact on ADC accuracy; can this be specified/estimated?
  3. Are there other side-effects to consider when the duty-cycle is outside of the typical range?

Any help is appreciated. Thanks.

  • 0
    TI__Genius 17125 points

    Hello Michael,

    The limits are supposed to be 40% to 60% but in reality it will probably function fine to 30% to 70% or more, but we have not characterized the part under those conditions.

    Since the conversion is triggered off the rising SCLK edges, the duty cycle will not have an impact on the conversion.  You do need to be sure that the duty cycle chosen will not cause you to violate the timing requirements for DI, DO and CSb.