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ADS1298: Internal Test Signal

Sofia Rafael
Prodigy 180 points
Part Number: ADS1298

Hello,

I have been trying to implement the internal test signal of the ADS1298 but I am having issues with it.

1- My register codes for the internal signal generation:

[0x41, 0x00, 0x85]
[0x42, 0x00, 0x10]
[0x43, 0x00, 0xC8]
[0x45, 0x0B, 0x05]

2- The results I am getting:

Questions:

1- Why is the test signal only 0.1mV in amplitude? (If I am using the internal reference to 2.4V and gain 6)

1.1 - Why is the signal deviated from 0V?

2- Why is only channel 1 configured for the test signal? (The other channels don't have the correct signal)

3- The spikes I am gessing are the effect of corrupted data from the readings I am acquiring, since some times the DRDY signal goes low during one reading.

4- My internal noise measurements are also deviated from 0V, why is that?

Thank you very much in advance,

Best,

Sofia

----

I have valid readings of the devices ID, I have validated the check points of the circuit, followed the startup advices.

I have nothing connected to the analog input pins of the ADS1298.

I have verified my conversion code from this explanation:

e2e.ti.com/.../2856893

  • 0
    TI__Guru**** 180931 points

    Hello Poster!

    Our support staff is taking time with their families for the Independence Day holiday here in the US.  It may be July 8th before we can get back to you with help on your query.  We apologize in advance for the delay and will get back to you as soon as possible.

  • 0
    TI__Guru 66256 points

    Hello Sofia,

    Thank you for your post.

    Based on the register settings you provided, it looks like you are not writing to the CHnSET register addresses correctly. The second byte in the command represents the number of registers to write minus 1. So to write to all 8 channel registers, the second byte must be 0x07. The remaining bytes in the command must contain the value to be written for each register. To write "0x05" to all 8 channel registers, the correct command would be:

    0x45 0x07 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05.

    I also noticed that you appear to be missing data in some places. This can happen when a new sample is ready to read (indicated by the /DRDY falling edge), but you are still reading old data. Make sure your SCLK frequency is fast enough to read all channels of data plus the STATUS word in between consecutive /DRDY falling edges.

    As far as why the amplitude and offset look incorrect, we'd have to look at the raw ADC data (in hex or decimal format). Can you save ~500 samples to a text file for just one channel of data?

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 180 points

    Hello Ryan,

    Thank you for your reply.

    1. You were correct, I changed the registers and If started responding for the other channels With the test wave, but with different offsets. Just as an example in this image are channel 0 and 1.

    2. About the missing data and weird peaks I will check that (I didn't have time today to reconfigure that, I think that tomorrow I will be able to correct that and will update this thread)

    3. I have attached the hexadecimal and voltage convertion for one channel in the internal noise test mode and the test signal mode.

    Thank you very much in advance,

    Best,

    Fullscreen noise_signal.txt Download 
    
                          

2019-07-09 02:43:05.847133
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    Fullscreen noise_signal_HEX.txt Download 
    
                          

2019-07-09 02:43:05.859731
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    Fullscreen test_signal.txt Download 
    
                          

2019-07-09 02:49:49.484455
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    Fullscreen test_signal_HEX.txt Download 
    
                          

2019-07-09 02:49:49.495454
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    Sofia

  • 0 in reply to Sofia Rafael
    TI__Guru 66256 points

    Hello Sofia,

    I was able to convert the raw data files (HEX format) and plot the results. The data and waveforms looks the same as what you provided.

    Are you certain this is how the raw data is coming out of the ADS1298? Are you by chance truncating or shifting the data somehow in memory? If you multiply the test signal data by a factor of 8 (i.e. bit-shift the data to the left 3 places), you achieve a signal from 0 to 1 mV (ignoring the spikes from misreading samples). This seems to correct the amplitude for the positive half of the test signal, but the negative half is still close to 0 V. It should reach -1 mV on the negative half of the signal (i.e. amplitude should be 2 mVpp).

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 180 points

    Hello Ryan,

    Thank you very much for your response.

    An example of some raw data is this:

    [192, 0, 0, 0, 10, 249, 255, 254, 231, 0, 15, 124, 255, 242, 159, 255, 246, 74, 0, 15, 86, 0, 12, 2, 0, 18, 101] --> So the numbers are in decimal

    The 24bit results for each channel are:

    0xaf9
    0xfffee7
    0xf7c
    0xfff29f
    0xfff64a
    0xf56
    0xc02
    0x1265

    Which are then converted to volts as you verified in the previous message. 

    So I don't see any shifting or truncation. Since the amplitude ranges differ from channel to channel (image in the previous post) is it possible that this is due to the test pace pins being connected (Problem identified in here ?

    Also, you say about the 2mVpp signal. Shouldn't it be 1mVpp? As Vref / 2400 = ( Vrefp-Vrefn )/2400 and  Vrefp-Vrefn = 2.4 as stated in table 7.3 Recommended Operating Conditions

    Thank you very much, your input has been very helpfull,

    Best,

    Sofia

  • 0 in reply to Sofia Rafael
    TI__Guru 66256 points

    Hi Sofia,

    The test signal amplitude described in the CONFIG2 register table is the peak amplitude, not peak-to-peak. This signal is connected to the PGA inputs, so the ADC will actually convert the 1-mVp test signal multiplied by the PGA gain.

    For example, please see the plot below taken from the ADS1298ECGFE-PDK. I've configured Channels 1-7 to use the internal test signal with 1 mV amplitude. Each channel is configured for a different gain (1, 2, 3, 4, 6, 8, 12 V/V, in that order). Clearly there is some offset on some channels, but the peak-to-peak amplitude is correct.

    As a side note - when I converted the raw data to Output (mV), I was using an LSB size of 47.68 nV. This was calculated as 2xVREF / Gain / (2^24-1). Therefore, the Output (mV) was being referred back to the input. The output-referred results are shown below.

    Regarding the related post you found, can you tell me how the TEST_PACE_OUT pins are connected in your circuit?

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 180 points

    Hello Ryan,

    The TEST_PACE_OUT pins at this point are connected to AVDD (3.3V) - even though they are not in this schematic.

    In the attachments are prints of the schematic I have mounted. (The resistors and capacitors to the left are not mounted, and no signals are being input at the analog terminals). DVDD is 1.8V.

    Thank you very much in advance,

    Best,

    Sofia