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ADS8353: SPI clock period and sample rate

Chris Wagner
Prodigy 30 points
Part Number: ADS8353

The datasheet appears to have conflicting information - it states that the ADS8353 is capable of 16 bits at 600ksps, and that it has a throughput time of 16.6us which is consistent.  But in the SPI clock specification it states that the minimum SPI clock period for the ADS8353 is 50ns and it requires a minimum of 49 clock pulses between samples (50ns x 49 = 2.45us or 408ksps).  The stated acquisition time of 730ns which is supposed to correspond approx to 16 clock cycles also agrees with the 50ns clock period.  So is this part capable of 600ksps (SPICLK period of 29.4ns), or only 408ksps (SPICLK period of 50ns)?

  • 0
    TI__Guru 66406 points

    Hello Chris,

    Welcome to our forum and thank you for your post.

    The ADS8353 is capable of full-throughput 16 bits @ 600 kSPS only when using the dual-SDO interface mode. As you can see in Table 15, the minimum SCLK period is 50 ns (i.e. the max frequency is 20 MHz). You need at least 48 clock falling edges to complete the frame plus one between frames, so 20 MHz / 49 = 408 kSPS max data rate in 32-clock, single SDO mode. In dual-SDO mode, the number of required clocks is only 32 (plus one between frames). Here, you can achieve the full 600-kSPS throughput.

    Best regards,