ADC12DJ5200RF: Upgrading the hardware from ADC12DJ3200 to ADC12DJ5200

Sunset, 

We are taking a look at your questions and will get back to you asap. 

Yusuf

Hi Sunset,

Which Jmode are your trying to run? Were you able to get JMODE1 to work on ADC12DJ3200? If yes I would start with JMODE1 since this mode is exactly the same between ADC12DJ3200 and ADC12DJ5200RF. Have you tried reducing the clock rate? What is your sampling frequency? 

Have you tested multiple units?

Regards,

Neeraj 

Thanks for the info.

so far only JMODE0 has been tested. Test on JMODE1 will be run soon.

Two units have been tested so far, with the same failure pattern.

Sampling rate 5.28Gsps.

Thanks,

SunSet

Hi Neeraj,

    Thank you for your quick response and my apologies for the delayed response on my part. We are using JMODE0. We never tried JMODE1. I just got the files for implementing JMODE1 and will try it out on Monday on the 5200 setup. Our sampling rate is 5.28 Gsps. This frequency works well with the 3200 board and as per the datasheet should work with 5200 in JOMDE1 since we are using in single channel mode. We have not tried reducing the clock rate yet. Do you recommend we try reducing the clock rate?

We have only 2 units populated with the 5200 chip. We tested both and failure results are pretty much the same for both.

We have also tried using some test patterns as described in the JTEST section. We tried K28.5, D21.5, steady high and steady low and slow clock pattern. In all of these tests, we notice on the scope that the specified pattern has other patterns preceding and following the desired pattern. Both 5200 boards exhibited similar behavior. According to the data sheet once a test pattern is initiated, it should continue but we don't see that, We see other patterns in the data stream coming out of the JESD lanes. Hope this information helps.

Best Regards,

Dhruva

Hi Dhruva,

Do you disable JESD by writing the value of 0x0 to register address 0x200 before enabling the test patterns?

Have you played with pre-emphasis register setting?  

SER_PE Address = 0x48

Here are config files you should use for JMODE0 and JMODE1. is 5.28 Gsps your clock rate or sampling frequency? Please try the register writes in your shown in attached files to program the ADC into JMODE0 and JMODE1 respectively. 

ADC12DJxx00RF_JMODE0.cfg

ADC12DJxx00RF_JMODE1.cfg

Regards,

Neeraj 

Hi Neeraj,

1.) Yes, we do disable JESD by writing a 0x00 to 0x200 register, then change the test mode to the desired pattern by writing to JTEST register 0x205 and then enable register 0x200 by writing a 0x01 to it.

2.) Yes, we have played with pre-emphasis settings and we did see the signal shape change. But even with different pre-emphasis values, we could not get the FPGA to sync with the ADC. We are observing the signal with a very high frequency scope and probed quite close to the ADC lane AC coupling capacitors. When we mentioned  that we are seeing other patterns, this observation is through the scope and not the FPGA. Moreover, the 3200 works with 0x00 pre-emphasis setting without any issues so we know that our board is not very lossy.

3.) 5.28Gsps is the sampling rate, not clock frequency and this works well for 3200.

4.) I did a dump of the registers from the ADC12DJ5200RF EVM board and also from our test board and did not notice significant differences. Most of the register settings that were different were expected or explainable. Some were due to different values in the ROM which we think will vary from chip to chip. I will once again go through the files you have sent and compare against them. May be I missed something.

5.) We tried JMODE1 for the JTEST test patterns case and still no luck with JESD sync. We cannot use JMODE1 fully for functional case as it is not availble on our FPGA, We would like to stick with JMODE0 if possible. We are fine with only 8 lanes of operation.

I am not sure if this information helps or not. Thanks a lot.

-Dhruva   

Hi Dhruva,

The reason I suggested to use JMODE1 instead of JMODE0 was to reduce  the serdes rate because i was not sure if your DEV clock was 5.28G or 2.64G. But since you mentioned your DEV clock is 2.64G so using JMODE0 should be fine. 

Here is what I would suggest to do next 

I would make sure your are following recommended intilization procedure mentioned in section 8.3 of the Datasheet. 

Once the device is programmed i would check register 0x208 BIT 2 This will indicate if your serdes PLL is locked. 

Regards,

Neeraj 

Hi Neeraj,

When I did a register dump from our 5200 board we get 0x04 from register 0x208. I get the same value from the EVM as well. That confirms that the PLL is locked on our board.

Is there a difference between the initialization procedure for the 3200 vs the 5200? What perplexes us is that everything works with the 3200 board we have but not the 5200. If the initialization procedure is different on the two chips, then that could be the problem. I will get back to you once i verify the initialization procedure.

-Dhruva

Good Morning Neeraj,

    I checked our code and here is our 5200 initialization steps. Overall it looks very similar to what you have. Are we missing any critical step that will cause malfunction?

ADC12DJ3200(false, 0x0000, 0xB0), // Do soft reset
ADC12DJ3200(false, 0x0200, 0x00), // Clear JESD_EN (always before CAL_EN)
ADC12DJ3200(false, 0x0061, 0x00), // Clear CAL_EN (always after JESD_EN)
ADC12DJ3200(false, 0x0201, 0x00), // Set JMODE0
ADC12DJ3200(false, 0x0202, 0x00 | (0x1F & FRAMES_PER_MULTIFRAME)), // FRAMES_PER_MULTIFRAME = 0x0E
ADC12DJ3200(false, 0x0204, 0x02), // Use SYNCSE input, 2s complement binary data, scrambler disabled
ADC12DJ3200(false, 0x0213, 0x07), // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
ADC12DJ3200(false, 0x0048, 0x00), // Set serializer pre-emphasis to 0
ADC12DJ3200(false, 0x0061, 0x01), // Set CAL_EN (always before JESD_EN)
ADC12DJ3200(false, 0x0200, 0x01), // Set JESD_EN (always after CAL_EN)
ADC12DJ3200(false, 0x006C, 0x00), // Set CAL_SOFT_TRIG low to reset calibration state machine
ADC12DJ3200(false, 0x006C, 0x01), // Set CAL_SOFT_TRIG high to enable calibration

-Dhruva

Hi Neeraj,

   Attached are a some scope plots from lane A0 when running the JTEST K28.5. This is what we are seeing on our scope. Would it be possible for you to probe your 5200 board and see what comes out when you put the chip into K28.5 test mode. I think that is where we need to start. K28.5_from_ADC12DJ5200RF.pdf

Hi Neeraj,

     Today, we also collected JTEST K28.5 from one of our 3200 boards. We see a continuous stream with no interruptions with other patterns. This is exactly what we expect to see from the 5200 board as well. We used the exact same code and firmware for this test. The three images are K28.5 at 3 levels of zoom on the time axes on the scope. 

-DhruvaK28.5_from_3200.pdf

Hi Dhruva,

In the register sequence you send me for ADC12DJ5200RF. I did notice your are setting register 0x202 to the value of 0x00 which is not a valid value. Can you try setting it to the value of 0x3 which means you are setting K = 4?

Regards,

Neeraj

Hi Neeraj,

    For register 0x202, the statement in code is: 

 0x00 | (0x1F & FRAMES_PER_MULTIFRAME)

where FRAMES_PER_MULTIFRAME is set to 0x0E. I am not sure why our programmer chose to write it in this fashion but I believe it is logically correct. It is essentially setting the value to of register 0x202 to 0x0E.

I hope this helps.

-Dhruva

Hi Neeraj,

    As per the data sheet the K parameter for JMODE 0 and JMODE1 is min:step:max is 3:1:256. The datasheet says that the step size is 1 which would seem to suggest that an odd value is permissible. Am I looking at the correct datasheet? The datasheet I am looking at is SLVSEN9 –APRIL 2019. I got it from TI website.

In any case, the setting of 0x0E works on the 3200 board we have.

I will nevertheless try out the K value you suggested and get back to you soon.  Thanks a lot.

Best Regards,

Dhruva

Hi Dhruva,

Do your supply currents (VA19, VA11, & VD11) look reasonable compared to the ADC12DJ3200 hardware? JMODE0 in the ADC12DJ5200RF is similar, but not identical to the ADC12DJ3200.  The only thing I notice is that you are not using scrambling and you are not explicitly setting your K-1 (KM1) value.

Edit - I was looking at this post yesterday and did not refresh it.  Looks like Neeraj already found the solution

ADC12DJ3200 JMODE0 valid K values: 3:1:32

ADC12DJ5200RF JMODE0 valid K values: 4:2:256 - the datasheet requires an update

Regards,

Kyle

Hello Kyle, Neeraj,

   We really appreciate your collective thinking. But let us take a step back and go back to the oscilloscope plots I had attached a few days ago. The scope plot for both 3200 and 5200 were provided. The tests we are running are some of those described in the JTEST. When using the test patterns in JTEST, none of the multiframe etc. matter as the output from JESD lanes are simply a continuous stream of the specified pattern like K28.5 and D21.5 etc. We are seeing this pattern on the 3200 plots but not on the 5200 scope plots. When using JTEST, we are not using any JESD communication protocol per say. The JTEST signal from the 5200s are not as expected. 

Although the multiframe KM1 setting does not matter for JTEST, we have however verified that we are setting the register to 0x0E during initialization by doing a register dump. Although this corresponds to an odd number of multiframe, Table.22 in the data sheet does indicate that odd values are valid for JMODE0 and JMODE1 (3:1:256  -> step size of 1). If the datasheet is correct, then I don't think this is a problem.

The currents on the two 1.1V supplies were 1.1A and 1.4A . We have no way to measure the 1.9V since it is derived on a system level supply that also powers other stuff on the board. The currents did not look too abnormal for VD11 and VA11.  We expect soemwhat higer current from the 5200.

Could it be that the silicon samples we got were somehow defective? We may be able to provide Lot and Date codes for it if it helps. Another option is if we take the chip out of our board and send them back to you, would it be possible for you to check it out?

Once again I am extremely grateful to the entire TI team for the effort in trying to resolve this mysterious problem. Thank you and looking forward to hearing from you regarding JTEST behavior.

Best Regards,

Dhruva

Hi Dhruva,

There is a typo in the datasheet for valid K value. The valid K values are 4:2:256. So please try the K value I suggest in the earlier post. If this doesn't help. You can send the couple of ICs back to us and we can take a look at them.  

Regards,

Neeraj 

Hello Neeraj,

    Thanks you for pointing out the datasheet typo. We will try out the the multiframe parameter change to see if it does anything. I am consulting with our SW engineer and FPGA engineer regarding this.

-Dhruva 

Hello Neeraj,

     We have tried the KM1 parameter of 0x0D like you suggested and guess what. It worked!. We were able to get JESD sync and the ADC is now functional. However there was something peculiar that happened. We did not try 0x0D initially. Given what you mentioned valid K values of 4:2:256, we tried 0x07 first since that would also be a valid value. However, it did not work initially. Then we tried 0x0D and it worked. After trying 0x0D, we went back to 0x07 and this time 0x07 also worked. So it would seem that 0x0D seems to have cleared some bad state in the chip that was not being cleared with a smaller setting. We can't quite explain that. Our expert engineer had been looking at our board for the past couple of days as well. He reported that when JESD sync was failing, he had noticed that the LINK_ALM was being set and after the 0x0D multiframe value, LINK_ALM is cleared.

I want to take this opportunity to thank you and your team for your tireless effort in resolving this problem for us. We had been stumped over this for the past 2.5 months.  Your help is really appreciated by our team. Thank you once again.

If it is OK, we would like to keep this post open for another couple of days so that we can try out our new 5200 fix in a bit more detail. If nothing come up in a couple of day related to this issue, you may certainly close this as solved.

Best Regards,

Dhruva

Hi Dhuva,

Glad to hear things are working on your setup. Regarding the issue where you were not able to get the sync with 0x202 set to 0x07 initially. Here are my thoughts. I think maybe register 0x200 was not set to 0x00 before change register 0x202 (KM1).

Regards,

Neeraj