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DAC38RF82: Providing single ended DACCLK before RSETB togling

Kazuhiko Hirano
Genius 15098 points
Part Number: DAC38RF82

Hello,

 

My customer would like to use single ended DACCLK.

However, default of SEL_EXTCLK_DIFFSE bit of CLK_PLL_CFG register is 0 = differential.

The Figure 141 in the datasheet says “Provide a clock to the differential or single ended clock input” then “Toggle RESETB pin low then high (recommended pulse duration >10us)”.

Even default is differential DACCLK, providing single ended DACCLK before toggling RESETB is really OK?

DAC38RF8X start up propery?

 

Best regards,

 

K.Hirano

  • 0
    TI__Guru* 91947 points

    Hirano,

    After you power up the system and provide the single-ended clock to the DAC, you will issue a hard reset to the DAC. Right after this, the next command will be to write to misc conf register 0x31 to switch to single-ended clock mode. The next step will be to do the fuse auto load followed by the remaining register writes.

    Using the attached config file, I was able to test this with the TI DAC EVM.

    Regards,

    Jim

    se_test.cfg