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Original question:

TINA/Spice/ADC12DL3200: SYSREF processing activity

TINA/Spice/ADC12DL3200: ADC12DL3200: SYS_REF and SYS_POS problems

daniele sassaroli
Intellectual 650 points
Part Number: ADC12DL3200
Other Parts Discussed in Thread: TINA-TI

Tool/software: TINA-TI or Spice Models

Hi Jim,

I had the time to execute the test that Paul had requested.

I send 10  SYS_REF impulses and read the SYS_POS registers.

I executed this sequence a lot of time.

The result is contained in the attached file.

You can verify that the SYS_POS Windows are not stable but change. This characteristic
is non a problem when the ADC clock is 1 GHz, while it is a problem when the ADC clock is 2 GHz.

The SYS_POS Windows have different positions that continuosly change (the LSB is 77 ps).

I think that the instability is not a consequence of uncontrolled clock division because the different
positions are really near.

Can yon explain me the functionality of the SYS_POS window function?

Do you have other suggestions to determine the cause of the SYS_POS window change?

I look forward to hearing from you,

Regards,
Daniele

Fullscreen SYSREF_POS11-07-19.txt Download 
Sequence of acquisiition of the SYSREP_POS without changing SYSREF_SEL (SYSREF_SEL = 0)
Sampling frequency 2 Gs/s, ADC clock frequency 1 GHz
Four different ADCs are used.
First column:  number of acquisition
second to fifth column: SYSREF_POS values for ADC#0 to ADC#3
Each row reports one acquisition, the procedure to acquire is as follows:
1 - Write SYSREF_SEL = 0 il all the ADCs
2 - Apply 10 rising edges of SYSREF
3 - Read SYSREF_POS from alla ADCs and report the values in the row 1
4 - Apply 10 rising edges of SYSREF
5 - Read SYSREF_POS from alla ADCs and report the values in the row 2
Repeat step 4 and 5 until the row 50.


            ADC#0                       ADC#1                       ADC#2                       ADC#3
 # 76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210  
                                                                                                                 
 1 110000000000001100000001    100000000000011000000001    100000001100000000000011    110000000000000110000001
 2 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
 3 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
 4 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
 5 110000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
 6 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
 7 110000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
 8 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
 9 110000000000001100000001    100000000000011000000001    100000001100000000000001    110000000000000110000001
10 110000000000001100000001    100000000000011000000001    100000001100000000000011    110000000000001100000001
11 100000000000011000000001    100000000001100000000001    100000001100000000000011    100000000000001100000001
12 111000000000000110000001    100000000000001100000001    100000000011000000000001    111000000000000011000001
13 100000000000110000000001    100000000001100000000001    100000001100000000000011    100000000000011000000001
14 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
15 110000000000001100000001    100000000000011000000001    100000001100000000000001    110000000000001100000001
16 111000000000000110000001    100000000000001100000001    100000000110000000000001    111000000000000110000001
17 110000000000001100000001    100000000000110000000001    100000001100000000000001    100000000000001100000001
18 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
19 100000000000110000000001    100000000001100000000001    100000000110000000000001    100000000000011000000001
20 111000000000001100000001    100000000000001100000001    100000000110000000000001    110000000000000110000001
21 100000000000110000000001    100000000001100000000001    100000011000000000000011    100000000000011000000001
22 110000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
23 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
24 110000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
25 100000000001100000000001    100000000011000000000001    100000011000000000000111    100000000000011000000001
26 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
27 100000000000011000000001    100000000000110000000001    100000001100000000000001    100000000000001100000001
28 110000000000001100000001    100000000000011000000001    100000001100000000000001    110000000000000110000001
29 100000000000110000000001    100000000001100000000001    100000001100000000000011    100000000000001100000001
30 110000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
31 111000000000000110000001    100000000000001100000001    100000000011000000000001    111000000000000011000001
32 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
33 111000000000000110000001    100000000000001100000001    100000000110000000000001    111000000000000110000001
34 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
35 111000000000000110000001    100000000000001100000001    100000000110000000000001    111000000000000110000001
36 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
37 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
38 111000000000001100000001    100000000000011000000001    100000000011000000000001    110000000000000110000001
39 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
40 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
41 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
42 100000000000011000000001    100000000000110000000001    100000001100000000000011    100000000000001100000001
43 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
44 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
45 110000000000001100000001    100000000000011000000001    100000000110000000000001    110000000000000110000001
46 111000000000001100000001    100000000000001100000001    100000000110000000000001    110000000000000110000001
47 111000000000000110000001    100000000000001100000001    100000000110000000000001    111000000000000110000001
48 100000000001100000000001    100000000011000000000001    100000011000000000000111    100000000000110000000001
49 111000000000000110000001    100000000000001100000001    100000000110000000000001    110000000000000110000001
50 100000000000110000000001    100000000001100000000001    100000011000000000000011    100000000000011000000001
   
   76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210 
 F            |----|                     |----|                   |---|                            |----|

The row "F" indicates the "Forbidden zone", thia appear to be too large to support a sampling frequency of 4 Gs/s.
Some acquisitions 4 Gs/s was executd with the same procedure, tghe results are shown below:

            ADC#0                       ADC#1                       ADC#2                       ADC#3
 # 76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210  

 1 110000011000001100000111    101100000110000001100001    111000001100000110000011    100000110000001100000111
 2 110000011000001100000111    111111000110000001100001    101100000110000011000001    100000110000001100000111
 3 111000001100000110000011    100110000011000000110001    100110000011000001100001    110000011000001100000011
 4 101100000110000011000001    100011000001100000011001    100011000001100000110001    110000001100000110000001
 5 110000011000001100000111    101100000011000001100001    111000001100000011000001    100000110000001100000111
 6 101100000110000011000001    100011000000110000011001    100110000001100000110001    111000001100000011000001
 7 101100000110000011000001    100011000000110000011001    100011000001100000110001    111000001100000110000001
 8 101100000110000011000001    100011000000110000011001    100011000001100000110001    111000001100000110000001
 9 101100000110000011000001    100011000001100000011001    100110000011000001100001    110000001100000110000011
10 111000001100000110000011    100110000011000000110001    101100000011000001100001    100000011000001100000111
11 111000001100000110000011    100110000011000000110001    100110000011000001100001    110000011000001100000011
12 110000110000011000001101    111000000110000011000001    111000001100000110000011    100000110000011000001101
13 111000001100000110000011    100110000011000000110001    101100000110000011000001    100000011000001100000111
14 101100001100000110000011    100011000001100000011001    100110000011000001100001    110000001100000110000011
15 111000011000001100000011    101100000011000001100001    101100000110000011000001    100000011000001100000111
16 100000110000011000001101    111000001100000011000001    111000001100000110000011    100001100000011000001101
17 111000001100000110000011    100110000011000000110001    101100000110000011000001    100000011000001100000011
18 111000000000100010000011    100110000001100000110001    100110000011000001100001    110000011000000110000011
19 101100000110000011000001    100011000001100000011001    100110000011000001100001    110000001100000110000011
20 101100000110000011000001    100011000001100000011001    100110000011000001100001    110000001100000110000011
21 111000001100000110000011    100110000011000000110001    100110000011000001100001    100000011000001100000011
22 100001100000110000011001    110000001100000110000001    110000011000001100000111    100011000000110000011001
23 110000011000001100000111    101100000110000001100001    101100000110000011000001    100000110000001100000111
24 101100000110000011000001    100011000000110000011001    100110000011000001100001    111000001100000110000001
25 111000001100000110000011    100110000011000000110001    101100000110000011000001    110000011000001100000011
26 101100001100000110000011    100011000001100000110001    100011000001100000110001    110000001100000110000011
27 110000011000001100000111    101100000011000001100001    111000001100000011000001    100000110000001100000111
28 110000011000001100000111    101100000011000001100001    101100000110000011000001    100000011000001100000111
29 111000001100000110000011    101100000011000001100001    100110000011000001100001    100000011000001100000011
30 101100000110000011000001    100011000001100000011001    100110000011000001100001    110000001100000110000011
31 101100000110000011000001    100011000001100000011001    100110000011000001100001    110000001100000110000011
32 111000011000001100000011    101100000011000001100001    101100000110000011000001    100000011000001100000111
33 101100000110000011000001    100001100000110000001101    100011000001100000110001    111000001100000011000001
34 100110000011000001100001    100001100000110000001101    100011000001100000110001    111000000110000011000001
35 100000110000011000001101    111000000110000011000001    110000001100000110000011    100001100000011000001101

   76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210    76543210FEDCBA9876543210 
 F         |--------------|            |----| |-----|              |---| |----| |-             --| |----| |---

Looking at the "Forbidden zone", we can note that:
1 - No valid position for SYSREF_SEL are available for ADC#0
2 - Very narrow zones are available for the other ADCs.

  • 0
    TI__Guru* 91947 points

    Daniele,

    Jim B is no longer with TI. Please send some background information regarding this post and I will try to direct your questions to someone who may be able to help you.

    Regards,

    Jim

  • 0
    TI__Guru* 91947 points

    Daniele,

    This from the design team:

     

    1. High jitter of SYSREF wrt. to clock, based on the dirty region moving  around from sequential SYSREF_POS read-backs.  This is not surprising if SYSREF is created by an FPGA.  We recommend using the LMK048xx families to distribute both clock and SYSREF.

    2. For the higher clock rates (4 GSPS, Fclk=2GHz) it appears you are using zoom=0 (based on 77ps per step from his data), making it difficult to find a suitable window, due to the coarse resolution.  Try using zoom=1 for higher clock rates.  This is set by bit 4 in Clock Control Register 0 (address = 0x029).   However, this won’t solve his root problem, which is the high SYSREF jitter.

     

    When clean clocks are used, the windowing is very stable for repeated captures even in the presence of large temperature changes; please see data  taken below with a 3.2 GHz clock. 

     

    Capture         ADC 0                                                           ADC 1                                                            ADC 2                                                ADC 3

    33       101100000110000011000001    100001100000110000001101    100011000001100000110001    111000001100000011000001

    34       100110000011000001100001    100001100000110000001101    100011000001100000110001    111000000110000011000001

    35       100000110000011000001101    111000000110000011000001    110000001100000110000011    100001100000011000001101

     

    Note also the very high correlation between the windowing for all ADCs, showing that it isn’t the ADCs which are “jittering”, rather the SYSREF signal (wrt clock).

     

    As a side note, automatic SYSREF calibration uses averaging, and is therefore much more tolerant to jitter of the SYSREF signal (wrt clock).  The problem is that the jitter is so high that even the near-perfect adjustment of the SYSREF capture obtained with automatic SYSREF calibration doesn’t get around the problem that the jitter is so high, that there is no guarantee that the ADCs align if the SYSREF pulse used to align the ADCs is an outlier.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 650 points

    Hi JIm,

    in the past email I described the architecture of the ADC chain.

    I use a T&H + ADC chain and the T&H works at 4 GHz. The TI clock components
    don't work at 4000 MHz and I can't use the LMK480XX in my design.

    The SYSREF signal is generated by the FPGA. The SYSREF is clocked with a precision
    TCXO external clock. I've also measured the SYSREF with an high speed oscilloscope,
    and I've verified that the signal is really stable.

    Regards,

    Daniele Sassaroli