DAC8811: DAC output update timing

toshi-e2e

Part Number: DAC8811

Hi all,
I have a question about the update timing of DAC output.

The below section of DAC8811 datasheet described that when CS sets to high the new data from the serial register is loaded to DAC register.

However, the section of 8.5.1 DAC8811 Input Shift Register described that the DAC output is updated on 16th rising edge of SCLK as below;

Which is the correct behavior?

Regards,
Toshi

over 6 years ago

0 Uttam Sahu over 6 years ago

TI__Genius 14220 points

Hi Toshi-san,

Thank you for your query. The DAC implements two registers: one for capturing (buffer register) and another for updating (data register) the data. The buffer register is a FIFO that takes the data in bit by bit on every clock rising edge. The data is processed at the rising edge of /CS and is passed to the data register if only the data is valid. Or else, the data is discarded.

Hope that answers your question.

Regards,

Uttam Sahu

Applications Engineer, Precision DAC

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DAC8811: DAC output update timing