AFE5851: Synchronized sampling over multiple ADCs

Peter Jancso

Part Number: AFE5851
Other Parts Discussed in Thread: CDCLVD1216, AFE5832LP, AFE5816

Hi,

We have a design with multiple AFE5851 devices. They receive the same sample clock of 20 MHz and they generate their on 10 MHz frame clock.

However we have observed that the frame clocks are not in phase. See the picture below (ignore the labels) which shows the frame clock of 4 different AFE5851.

Since I believe the frame clock is in tight relation with the actual sampling moment, two of the above ADCs sample 50 ns later, then the other two.

Is there any way to synchronize them to each other? I was trying to achieve this with centrally controlled PDN signal, but it was not successful. The biggest

problem is, that after power-up different AD converters are synchronous than previously, which add random 50 ns variance between these devices.

thank you for the help.

regards,

Peter

over 5 years ago

0 Praveen Aroul over 5 years ago

TI__Mastermind 49746 points

Hi Peter,

It seems like there is some phase difference between the sample clocks going to the four AFEs which is, in turn, causing the frame clocks to go out of sync.

Probe the clock pins at the input of the AFEs with respect to the frame clocks to determine the propagation delay between the input clock and the frame clock.

0 Peter Jancso over 5 years ago in reply to Praveen Aroul

Intellectual 310 points

Hi Praveen,

I do not think phase difference between sample clocks are the root cause. They are all generated by CDCLVD1216 and their trace-length are matched.

For reference I have measured two frameclock to their corresponding sample clock (channel 1 and channel 2 are frame clock, while channel 3 and channel 4 are their sample clock respectively).

As you can see, despite the fact the sample clock are in phase, their frame clocks are not. I guess it depends on when they actually wake up and which rising edge their PLL are actually locked onto. We have a centrally controlled PDN signal, but I have measured very different wake up times over our ADCs.

I have also found one thread discussing this:

https://e2e.ti.com/support/data-converters/f/73/t/369089?tisearch=e2e-sitesearch&keymatch=afe5851

I am not sure whether or not this is something recently being worked on in TI.

Peter

0 Peter Jancso over 5 years ago in reply to Peter Jancso

Intellectual 310 points

Hi Praveen,

Did you have time to look into this?

Thank you.

Best regards,

Peter

0 Praveen Aroul over 5 years ago in reply to Peter Jancso

TI__Mastermind 49746 points

Hi Peter,

Can you try applying a pulse signal on SYNC pin with timing met w.r.t. ADC clock?

0 Peter Jancso over 5 years ago in reply to Praveen Aroul

Intellectual 310 points

Hi Praveen,

is it somewhere specified in the datasheet, what the minimum pulse is and which clock it shall be synchronized? I have failed to find this information.

thank you.

Regards,

Peter

0 Peter Jancso over 5 years ago in reply to Peter Jancso

Intellectual 310 points

Hi Praveen,

I made a couple of tests with SYNC pin and does not seem to solve the synchronization problem. See below.

where channel 1 is SYNC, channel 2 is AD_CLK, while channel 3 and 4 are two different AD converters' frame clock. The two picture have been captured

a power cycle apart.

Best regards,

Peter

0 Praveen Aroul over 5 years ago in reply to Peter Jancso

TI__Mastermind 49746 points

Hi Peter,

I am checking with the designers regarding this and will keep you posted by tomorrow or by early next week.

0 Praveen Aroul over 5 years ago in reply to Praveen Aroul

TI__Mastermind 49746 points

Hi Peter,

I checked with the design team.

Unfortunately, there is no way to synchronize the FCLK (divider) across devices.

Using the frame clock only data has to be interpreted in FPGA. (https://e2e.ti.com/support/data-converters/f/73/t/369089)

0 Peter Jancso over 5 years ago in reply to Praveen Aroul

Intellectual 310 points

Hi Praveen,

It is not about we are not able handle this in the FPGA. More like that AD converters samples in different time, and it is not consistent after power cycle.

Before I close this ticket, would you please recommend an ADC with similar parameters and device synchronization capability?

thank you,

Peter

0 Praveen Aroul over 5 years ago in reply to Peter Jancso

TI__Mastermind 49746 points

Hi Peter,

AFE5832LP will be the best choice if your system needs 32 channels.

For 16 channels, you can look at AFE5816.

Data converters

Data converters forum

AFE5851: Synchronized sampling over multiple ADCs