AFE5851: Synchronized sampling over multiple ADCs

Hi Peter,

It seems like there is some phase difference between the sample clocks going to the four AFEs which is, in turn, causing the frame clocks to go out of sync.

Probe the clock pins at the input of the AFEs with respect to the frame clocks to determine the propagation delay between the input clock and the frame clock.

Hi Praveen, 

I do not think phase difference between sample clocks are the root cause. They are all generated by CDCLVD1216 and their trace-length are matched.

For reference I have measured two frameclock to their corresponding sample clock (channel 1 and channel 2 are frame clock, while channel 3 and channel 4 are their sample clock respectively).

As you can see, despite the fact the sample clock are in phase, their frame clocks are not. I guess it depends on when they actually wake up and which rising edge their PLL are actually locked onto. We have a centrally controlled PDN signal, but I have measured very different wake up times over our ADCs.

I have also found one thread discussing this:

https://e2e.ti.com/support/data-converters/f/73/t/369089?tisearch=e2e-sitesearch&keymatch=afe5851

I am not sure whether or not this is something recently being worked on in TI.

Peter

Hi Praveen, 

Did you have time to look into this?

Thank you. 

Best regards, 

Peter

Hi Peter,

Can you try applying a pulse signal on SYNC pin with timing met w.r.t. ADC clock?

Hi Praveen, 

is it somewhere specified in the datasheet, what the minimum pulse is and which clock it shall be synchronized? I have failed to find this information.

thank you. 

Regards, 

Peter

Hi Praveen, 

I made a couple of tests with SYNC pin and does not seem to solve the synchronization problem. See below.

where channel 1 is SYNC, channel 2 is AD_CLK, while channel 3 and 4 are two different AD converters' frame clock. The two picture have been captured 

a power cycle apart. 

Best regards, 

Peter

Hi Peter,

I am checking with the designers regarding this and will keep you posted by tomorrow or by early next week.

Hi Peter,

I checked with the design team.

Unfortunately, there is no way to synchronize the FCLK (divider) across devices.

Using the frame clock only data has to be interpreted in FPGA. (https://e2e.ti.com/support/data-converters/f/73/t/369089)

Hi Praveen, 

It is not about we are not able handle this in the FPGA. More like that AD converters samples in different time, and it is not consistent after power cycle.

Before I close this ticket, would you please recommend an ADC with similar parameters and device synchronization capability?

thank you, 

Peter