Part Number: ADS131M04EVM
Hello,
I'm having an odd issue with my ADS131M04EVM board when trying to read the ADC channel outputs. On all enabled channels, I am seeing a cycle consisting of 5 values that are all more or less consistent, and only 1 is correct. The table below illustrates readings from channel 0 with input values of .054mV and .277mV respectively showing 2 cycles with the "good" values highlighted.
| .04219 | .10078 | .26484 | .18984 | .19219 | .04219 | .10313 | .25781 | .18984 | .19219 |
| .28359 | .42656 | .19219 | .4125 | .25781 | .28594 | .42422 | .19219 | .41016 | .25547 |
I have my board configured to have a data rate of 300sps, which I am achieving by having CLKIN be 4.915MHz with an OSR of 8192. The SPI trace below shows that conversion data is ready and is being output at a rate of 300sps. With a gain setting of 128, I have an FSR of 9.375mV and I am using the equation ((FSR/2^23)*raw adc output)*1000 to get my output in mV.
I can't find anything to explain why I am seeing this error, the data is being read out as expected and starts with the status register value and DRDY goes high when the last byte is clocked out. I also looked at the raw ADC values and they follow the exact same pattern, so the error isn't caused by my conversion of the output. Any insights into what is causing this would be greatly appreciated, as I am stumped right now.
