Part Number: ADS1278
i want to sample a standard 19.2k sine wave by using ads1278 in the following configure.
|
Name |
Parameter |
note |
|
FCLK |
36MHz |
oscillator |
|
FORMAT[2:0] |
011 |
Frame-Sync TDM |
|
MODE[1:0] |
00 |
High-Speed |
|
Vref |
2.048V |
|
|
DVDD |
2.0~2.2V |
adjust |
|
CLKDIV |
1 |
Fclk/Fdata=256 |
Because i want to use 38.4k sample rate to sample the 19.2k sine wave, so there should be 2 sample points in every cycle.But the real results don't like what i think.
The real results is listed as the follow figure.You can see that the sample points is not fixed as the same position.But i really don't know why the sample points can't be fixed as i want.
And the code is sample and listed below. The chip is TMS470.
void isr_38k4_timer(){
spi_send(0x00);
ad_read[0] = spi_read_buff;
delay(1us);
spi_send(0x00);
ad_read[1] = spi_read_buff;
delay(1us);
spi_send(0x00);
ad_read[2] = spi_read_buff;
ad_value = (ad_read[0] << 8) + (ad_read[1] << 8) + ad_read[2];
}
It has really confused my for a week. i want to know that this phenomenon is normal or not. And how could i solve this problem. THX!
