Good morning
I am trying to understand the definition of deterministic latency, and further dig in the JESD204.
I read the document slap159.
In this document the Latency overlap with the multi device synchronization, but I confirm I need to poin the latency question
On page 10 a good diagram is given.
In the picture the S2PO is the Latency as defined in the JESD204 sense.
In the chain of latencies the only unknown is the Lane Delay, the others should be repeatable.
In the picture the Link Latency is red outlined, it is not clear to me why.
1)) So my first question is: is the Lane Delay the only unknown latency in the chain? Or ADC Core Latency and the TX/RX Delay are to be considered as not predictable and repeatable??
2)) The other question: At the output of the Elastic Buffer the latency is made repeatable, correct???
Effectively I have a number of questions regarding the JESD204 I do not solve just reading the documentaion. I need to start testing this forum for now.
Thank You
Pietro
