DAC39J84: JESD clock

art arty

Prodigy 140 points

Part Number: DAC39J84
Other Parts Discussed in Thread: DAC38RF84

"JESD clock" description in DAC39J84 datasheet isn't accurate enough.

So I turned to DAC38RF84 datasheet and found "SERDES PLL REFCLK".

Do "JESD clock" in DAC39J84 and "SERDES PLL REFCLK" in DAC38RF84 have the same functionality?

Are "JESD clock" and DACCLK aligned in DAC39J84?

Do "JESD clock" frequency equal to fDATA?

over 6 years ago

0 dBrock over 6 years ago

TI__Genius 12780 points

Hi Art,

We are taking a closer look into your question, and will be back with you soon.

Best Regards,

Dan

0 jim s over 6 years ago

TI__Guru* 91947 points

4188.DAC38J84 Clock, PLL and SERDES Configuration.docxArt,

Please see attached document.

Regards,

Jim

0 art arty over 6 years ago in reply to jim s

Prodigy 140 points

Thanks for your answer, that helped me a lot.

But which clock "samples" samples that goes into interpolator?

0 jim s over 6 years ago in reply to art arty

TI__Guru* 91947 points

Art,

This would be the DACCLK.

Regards,

Jim

0 art arty over 6 years ago in reply to jim s

Prodigy 140 points

Thanks for your answer. I thought it should be something like DACCLK / N, where N is interpolation

Whereas DACCLK is clock that "samples" samples that goes into DAC after interpolator

Am I wrong?

0 jim s over 6 years ago in reply to art arty

TI__Guru* 91947 points

Art,

The interpolator block uses the DACCLK but it gets divided done to create another clock to register the input data at DACCLK / N rate. The data out of this block is at the DACCLK rate.

Regards,

Jim

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DAC39J84: JESD clock