I am interfacing an ADC08D1520 to a AvNet Picozed 7030 (http://zedboard.org/product/picozed). The Picozed is a SOM for the Xilinx Zynq chips.
We operate in 1:2 demultiplex mode. We take the 375MHz clock from the ADC into the FPGA. We divide the clock in half and run the FPGA at 187.5MHz. We have VHDL source to read the read and order 8 analog samples and send them to the ARM size of the Zynq for debug. We have extended control mode working and can enable/disable the test pattern.
We have one custom PCB board that works perfectly. The test pattern is correct for both I and Q channels. Since this board works well, I do not believe there is an issue with our VHDL source/FPGA logic.
We have several other custom PCBs. All of our other PCBs exhibit a similar problem where the test pattern is incorrect.
For the I channel, this is a sample dump (dump is via Unix command line utility od, first number is a byte offset, * indicates a repeated line):
0056236 02 04 fd fb 02 04 fd fb 02 04
*
0057044 02 04 fd f3 02 04 fd fb 02 04
0057056 02 04 fd fb 02 04 fd fb 02 04
*
0057114 02 04 fd f3 02 04 fd fb 02 04
0057126 02 04 fd fb 02 04 fd fb 02 04
We get see an occasional bit error where 'fb' is 'f3'. Although not shown above, we also see occasional bit errors where '04' is '00'.
For the Q channel, things are much worse:
0060530 01 03 01 03 01 03 f5 0e 09 03
0060542 01 03 01 03 01 03 45 02 01 03
0060554 01 03 01 03 01 03 f5 0e 01 03
0060566 01 03 01 03 01 03 f5 0c 01 03
0060600 01 03 01 03 01 03 e5 02 09 03
We do see '01' '03' as expected. We don't see 'fe' 'fc'. Also, '01' '03' repeats more often than expected. There are significant bit errors here.
If I run the exact same load with the exact same tests on my working board, I get no bit errors. The test patterns look perfect. If I run the above tests on other non-working boards, I get similar results. Q always looks worse than I.
Any suggestions or assistance in troubleshooting would be greatly appreciated,
Eric
