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DAC5681EVM: Recreating waveform with FPGA

Part Number: DAC5681EVM
Other Parts Discussed in Thread: CDCM7005, DAC5681Z

Hello,

I have used the TSW1400 to create a waveform with the DAC5681EVM board. A .csv file was created in MATLAB, and loaded into the High Speed Data Converter software. Its data rate was 250 mega samples per second. Once we got the register settings figured out, the waveform looked exactly like we wanted on the spectrum analyzer.

One odd but necessary part was setting the Y2 output (the one feeding back to the TSW1400) of the CDCM7005 to a 16 times divider.

I'm using a Cyclone V dev board now to try and recreate this waveform. I took the successful .csv file, converted into 2's complement memory file, and instantiated a ROM in the FPGA using it.

The FPGA code reads out the memory file and sends it to the DAC at 250MHz. I followed the Clock and Data Timing Diagram in Figure 42, page 34 of the DAC5681z datasheet. I made sure to save the DAC5681z register settings used with the TSW1400 and reload them for the FPGA. The only register change is reversing the data bus, due to the FPGA dev board HSMC pinout.

However, I cannot get the waveform to look anything close to correct. I'm using the same data to write to the DAC, but it's looking completely different.

Does anyone have any guidance?

Thank you!

  • Adam, 

    If you were able to use the TSW1400 with the DAC to successfully generate the waveform then there is likely something wrong with the Cyclone V dev board if you only see issues when using that. I would try using the original .csv file without converting to 2's complement to see if that makes a difference, other than that i would check with the the technical team that supports the Cyclone V dev board for further support. 

    Thanks

    Yusuf

  • As far as I can tell the Cyclone V dev board is fully functional.

    I'm wondering if there is a issue with my code implementation, or not using the correct clock speed when communicating with the DAC.

    The original .csv file is in decimal integer form, so I would have to do some sort of conversion for it to be used in a memory file.

  • Adam, 

    Then the problem is likely somehow related to clocking. Can you verify what the FPGA clock requirement is relative to the DAC clock & data clock for the dev board you are using? Can you verify on a scope that the FPGA is receiving a clock from the DAC?

    Yusuf