ADS54RF63: If Low Jitter Clock Solution For High-Speed must be used when set the sample rate to higher than 500Msps.

If Low Jitter Clock Solution For High-Speed must be used when set the sample rate to higher than 500Msps.

The datasheet shows this CLK solution is useful, but when I study the EVM boards design,I find they don't use this CLK solution. So can you tell me if this CLK solution is necessary?

Note: The EVM boards's I studied are "ADS5440/44/63/74 EVM" and "ADS54RF63-ADX4 Single-channel, 12-bit, 2.2 GSPS Evaluation Module".