DAC8742HEVM: about register access and CD timing when UART communication

Hello,

motoo nakayama said:

1. Is The UART possible to accese(read/write) registers like The SPI.
    It did not change the fifteenth RESET flag in modem status register [0xA0, 0x00, 0x00] (with READ flag)
    and change the RESET flag in reset register [0x07,0x00,0x01] by UART.

No - the UART is designed to be a very simple 1200 BAUD feedthrough, similar to the interfaces offered by conventional modems. The extended features are only available with the SPI interface.

motoo nakayama said:

2. CD rising edge shifts frequently When recieve the beginning FSK signal by UART.
    Show the attached PDF.
    Is there a way to steady it ?

I am not sure I understand the question. Are you referring to the phase difference for when the carrier detect signal is asserted in the two waveforms? Was this captured using internal or external filter / reference / clock components? 

Dear Duke,

Thank you for your reply.

BPF settings on DAC8742HEVM are JP9[2-3](internal) , JP10-11[2-3](C19), JP16[5-6](C24) and Internal BPF is enabled by JP18(2-3).

REF setting enables internal 1.5V REF at JP19[2-3].

CLOCK settings are JP1[1-2](Y1) and JP2[1-2](Y1) for HART clock.

waveforms in PDF show that CD rising edge on FSK signal is delayed once every 3 times.

at this time, UART is sending the same data every 1 sec.

Do you have any solutions ?

Motoo,

The figure on the right side of your slide is actually more representative of what we expect from the device and what is shown in the datasheet in Figure 11. I'm actually a bit more surprised by the image on the left in your attachment. Still, both are HART compliant as the specification gives up to 5 bits to assert a valid CD signal.