Other Parts Discussed in Thread: TRF3765, ADC12J4000, LMK04828
I am in the process of building a radar system using the ADC12J4000EVM mated with the TSW14J56 FPGA for the RX digital back end. In order to meet timing requirements with other components of the system, I have made a slight modification to the board to allow the TRF3765 PLL to be clocked by a 100 MHz input signal to the OSC_IN pin on the ADC12J4000 board rather than the on-board 100 MHz TXCO.
However, I realized that the SYSREF clock signal being generated by the LMK04828 does not have a deterministic phase relationship with the 100 MHz input signal between system resets due to the multiple clock multiplications and divisions occurring within the TRF3765 and the LMK04828. Since data is collected by the TSW14J56 on the edge of the SYSREF signal, it must have a deterministic timing relationship with the timing of the TX side of the system in order for pulses of the radar to have consistent timing between system resets.
Ideally, we would be able to use the SYNC pin on the LMK04828 to align the SYSREF clock with an external pulse. However, as far as I can tell on the schematic, the SYNC pin is directly connected through the FMC connector to the FPGA chip and is not really accessible.
Do you have any ideas for how we can achieve a deterministic phase relationship between the SYSREF signal and the input 100 MHz reference signal? We are okay doing some board modifications if necessary. Let me know if you need any clarification.