1.8V CMOS JEDEC standard calls VOL max 0.45V, VIL min 0.63V. This provides 0.18V noise margin.
However, ADS41B29 Low level input voltage max is only 0.4V. This is less than the guaranteed JEDEC VOL.
This makes it incompatible with Xilinx LVCMOS18 IO standard.
Yet the text indicates that it supports 1.8V CMOS logic.
