ADS1246/7/8 data sheet question - DOUT/DRDY

Scott Holmstrom

Other Parts Discussed in Thread: ADS1248

I'm looking for some clarification on the functionality of the ADS1248 DOUT pin. In the data sheet - SBAS426E (revised December 2010) - the DOUT/DRDY description on page 36 says the data is clocked-out on the rising edge of SCLK. The timing diagrams appear to contradict this, showing the clocking on the falling edge of SCLK. It is also the opposite polarity from the DIN pin, which is described and diagrammed as being clocked-in on the falling edge. Can anyone clarify the correct DOUT/SCLK relationship? Thanks!

over 15 years ago

0 Bob Benjamin over 15 years ago

TI__Guru** 113765 points

Scott,

It is actually correct, but I agree it is somewhat confusing. The data clocks out of the device on the rising edge(state change), but you want to capture on the falling edge (data stable).

Best regards,

Bob B

0 Scott Holmstrom over 15 years ago in reply to Bob Benjamin

Prodigy 50 points

Thanks Bob, That little bit of extra information makes all the difference. Regards, Scott

0 Tim Kirk over 15 years ago in reply to Bob Benjamin

Prodigy 70 points

Thanks for this bit of info. It wasn't clear in the datasheet, and I was seeing a very strange problem where the high bit of the high byte was always mirroring the high bit of the middle byte on my readings until I changed to capturing the bit on the falling edge.

Now, capturing the bits on the falling clock edge that problem is no longer presenting itself.

Tim Kirk

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ADS1246/7/8 data sheet question - DOUT/DRDY