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TLV5614: Initial output value problem

kevin p
Intellectual 470 points
Part Number: TLV5614
Other Parts Discussed in Thread: DAC60504

Hello team,

We are using TLV5614 DAC in one of our design, when I power on and power off the power supply repeatedly, and I found some TLV5614 have issues as below:

1. The VOUTA~D of TLV5614 output random voltage value when power on, the MCU doesn’t control the TLV5614 when power on. But the output voltage are 0~4.8V, which isn’t ~0V.

2. How does the TLV5614 power-on reset? Why the registers don’t be cleared when power-on.What conditions are required to power-on reset?

3. Is there any timing sequence requirement for the power supply and the reference voltage?

In my design, the AVDD and DVDD connect together to 5V, and the REF2.5V is powered by 5V, the rise time of 5V and REF2.5V are ~2ms.

4. In my design the control signals have 10k pull-up resistor to 3.3V, the 3.3V is powered by 5V,the rise time of 3.3V is ~2ms.

Is there any timing sequence requirement for the power supply 5V and control signal power supply 3.3V?

Attached is the circuit diagram. Please help to review, and give recommends and solutions.

Look forward to your support, as the project is urgent, please reply ASAP. Thank you.

Kevin

4087.SCH.pdf

  • 0
    TI__Genius 14220 points

    Hi Kevin,

    Thank you for your query. I am looking into your issue. Couldn't get much time today. I will get back on Monday.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DAC

  • 0 in reply to Uttam Sahu
    Intellectual 470 points

    Hi Uttam Sahu,

    Thank you for your support.

    Kevin

  • 0 in reply to kevin p
    TI__Genius 14220 points

    I pressed the resolved button by mistake for this thread. Sorry for that. This device doesn't need any power supply sequencing.

    Your circuit looks fine. So, I am doubting some device failure. Are you observing this failure on multiple boards and/or devices?

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Intellectual 470 points

    Hello Uttam,

    Thank you for your support.

    When the failure occurs, I power on and power off repeatedly, most of times the output is 0~4.8V, and very few times the output is ~0V.

    I found  ~80% of boards have abnormal initial values when power on and power off repeatedly.

    Even if the failed device, the DAC can be set normally, only the  initialization output is not ~0V when power on.

     

    How does the TLV5614 power-on reset?Could you contact your design engineer, what's the condition of the device power-on reset?

    Could you recommend the time sequence of DVCC, AVCC, REF2.5V and 3.3V(the voltage on the SPI interface) when power on?

     

    If the power on the SPI interface before the DVCC/AVCC/REF2.5V,does this can effect the power on reset?

    Does REF2.5V need to power on after DVCC/AVCC  has full powered?How long does REF2.5V should be delayed？20ms,50ms...

     

    Look forward to your reply.Thank you.

    Kevin

     

     

  • 0 in reply to kevin p
    Intellectual 470 points

    Hello Uttam,

    Is there anything updated? Could you help to resolve my issue.

    Thank you.

    Kevin

  • 0 in reply to kevin p
    TI__Genius 14220 points

    Hi Kevin,

    Sorry for the delay in the response. There is no power supply sequencing requirement for this device. However, you need to follow the ABS max requirements specified in the datasheet page 3. The reference input cannot be higher than AVDD even during the power ramp-up and ramp-down. There is no requirement of delay between the reference and any other power supply.

    The difference between AVDD and DVDD must be between +/- 2.8V even during power ramp-up/down. 

    Please check the above conditions. You might be violating one of them.

    Hope that answers your question.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Intellectual 470 points

    Hello Uttam,

    Thank you for your support.

    The built-in power-on-reset circuit in the TLV5614 to controls the output voltage after power on.

    How to ensure that the power-on-reset circuit operates correctly?

     

    If the  logic high voltages(3.3V)  applied to the logic input pins(SPI)  when power is not applied to AVDD and DVDD, the AVDD is connected with DVDD on the same power supply(5V).

    Does this affect the power on reset and the output isn't ~0V?

    Could you contact your design engineer to simulate it? I want to see the simulation results.

    Thank you.

    kevin

  • 0 in reply to kevin p
    TI__Mastermind 46290 points

    Kevin,

    The TLV5614 was released in 1998. Simulation results from design will be very difficult, if not impossible, to support given the age / accessibility of those old design tools and the number of times the database has probably been migrated from one server to the next - some linkages may be broken etc.

    You may consider looking at a more modern device. Not only would more robust simulation support be available, but in general we have made many improvements over the last 21 years which could be beneficial. It's also cheaper, so you get all of those benefits at a lower cost.

    kevin p said:
    If the  logic high voltages(3.3V)  applied to the logic input pins(SPI)  when power is not applied to AVDD and DVDD, the AVDD is connected with DVDD on the same power supply(5V).

    If this were to occur, the third condition in the Absolute Maximum Ratings table would be violated (Digital input voltage range = -0.3V to DVDD + 0.3V). There are internal ESD structures which would be forward biased and effectively "reverse power" the AVDD/DVDD digital cores, which would potentially impact the POR comparator circuit which would very likely corrupt latching the internal OTP memory which contains information like trim coefficients and what the DAC output should look like at start-up.

    Another item is that there is also potential for similar POR / OTP corruption if the power-supplies are not completely discharged. There is a fixed internal comparator threshold for the POR circuit with some fairly wide tolerance - if the supply does not completely discharge, or really more accurately go below the POR threshold for a long enough time period, the internal memory may not be reliably latched.

    More modern datasheets document this. You can see it in the DAC60504 datasheet in Figure 59 on Page 24.

    One, or both, of these issues are quite likely the root cause of what you are seeing.

  • 0 in reply to Kevin Duke
    Intellectual 470 points

    Hello Kevin,

    Thank you for your support.