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OMAP L138 and ADS1278 new design

Alberto Dassatti
Prodigy 40 points
Other Parts Discussed in Thread: ADS1278, CDCE906

Dear experts,

 

I'm in the design phase of a new board where the main components are OMAP L138

and ADS1278. We have some doubts and I hope your experience will help us highlight

possible problems. First of all our system has to adjust dynamically the

sampling frequency from few kHz to the top converter speed (144kSPS).

We checked the schematics of EVM module and carrier, but we still have

doubts both on hardware and software sides;

 

Here a list of questions.

 

Hardware:

 

1) On the ADS1278 datasheet (July 2009) at page 5 is stated DVDD has to be

between (1.65 - 1.95) V if fclk is less then 32.768 MHz and between

(2.0 - 2.2)V over that frequency. Does it imply DVDD has to be changed

dynamically? Can it be fixed at around 2 V in any case? Can you detail

possible drawbacks? In the ADS1278EVM DVDD is fixed at 1.8 V, does it mean

it cannot run at top speed?

 

2) Considering the interconnection between the converter and the processor

we are planning to use the McBsp port. We have few dubts regarding this

interconnection:

 

a) is the McBsp fast enough to manage continuously all the data acquired

by the converter? Would the McASP (we have few experience with it)

coupled with the converter in Discrete output mode a better solution?

 

b) Considering the McBSP case, what is the best topology for the clock generation.

Our first guess was using the schema at page 38 of the ADS1278 Datasheet

(is the flip flop necessary?). In this schema the CLKR is an output. Our doubt is: can the

L138 generates all the desired frequency on CLKR to drive the converter?

What will be the jitter on the generated clock? and the accuracy?

Unable to find out answers, we investigated the possibility of adding an

external programmable PLL (CDCE906 for example) to generate Clk and drive

with it both CLKR and SCLK. In this case we are able to generate all desired

frequencies, but the power budget is very critical for us. Is the external

PLL necessary?

 

Software:

 

1) We are planning to use the ARM side alone in the first stage. Our hope is running Linux

because we need some services (mainly networking and file system). Is there enough

horse power in the L138 to continuously acquire data at converter's top speed and

stream (eth) or store (sata, usb) them?

 

2) Is there around something similar to

http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_Multichannel_Audio_Serial_Port_%28McASP%29_Throughput_and_Optimization_Techniques

with benchmark, examples and suggestions for McBsp?

 

 

Best Regards,

A.

  • 0
    TI__Guru**** 180941 points

    Hi Albert,

    I'll look around for details on how to best support the ADS1278 with the OMAP L138.  I believe you would be better off using the McASP while running the ADS1278 is discrete mode.  The external PLL gives you the most flexibility in clock generation, using the internal clock may not provide all the discrete sampling frequencies you want/need.  With the McBSP option, we found the FF necessary in order to achieve the highest throughput rates in Frame Sync mode. 

    We'll get back to you with more detail soon.

  • 0 in reply to Tom Hendrick
    Prodigy 40 points

     

    Hi Tom,

    thanks for your answer.

     

    We are going to the McASP  + ADS1278 in discrete mode direction as you suggested.

    We still have some doubts on DVDD. Can you share any insight on that?

     

    Moving from McBSP to McASP we investigated the software support. As far as I know

    there is an audio driver in dvsdk 4_00_00_22 (sound/soc/davinci/davinci-mcasp.c). This

    works fine and provides all the support to the ALSA infrastructure. Due to the relatively

    high throughput ( > 27 Mb/s) we'd prefer run with something more "base line" and manageable;

    Do you know if any other driver is around or if there is any mmap() example dealing with multiple serializers

    and the MCASP?

     

    Regards,

    A.

  • 0 in reply to Alberto Dassatti
    TI__Guru**** 180941 points

    Alberto,

    The ADS1278 can be held at 2.0V DVDD operation while sweeping the CLK from 37MHz to 0.1MHZ.   The restriction here would be with the reference voltage, if the clock is >= 32.768MHz, then Vref is limited to 2.1V.  Unfortunately I don't know if there are any other drivers or mmap examples available, I have nothing specific for the ADS1278.  For generic code/driver examples, you might consider asking around in the OMAP forum.