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DAC38RF82: LANE error: frame alignment error and link configuration error

Wong
Intellectual 570 points
Part Number: DAC38RF82

Hello,There

    We are now debugging DAC38RF82, In the mode LMFSHD=82121 ,DAC is working good;But,In the mode LMFSHD=22210 DAC report link config, frame alignment errors.

 Design details:

(1)LMFSHD=22210;

(2)FDac(DACCLK)=5760M,External Diff Clk;

(3).Single DAC(DAC A)

(4) 1 IQ pairs

(5) 2 serdes lanes

(6)Interprolation=24

(7)output IF analog signal=1.7GHz

(8)sysref=10MHz

(9)FPGA  GTH refclk=120MHz

(11) K=24,RBD=23

QUESTION:

1. We read register  0x66 to 0x67; 

(1)register  0x66 is 0x2000;link configuration error

(2)register 0x67 is 0x6000;link config error, frame alignment errors.

2.there is no data output,Sync always from High to Low

Best Regards,

Wong

 

 

  • 0
    TI__Expert 4880 points

    Wong, 

    We are taking a look at this and will get back to you asap. 

    Yusuf

  • 0
    TI__Guru* 91947 points

    22210_mode_FS_5760_24x_Int.cfgWong,

    Please check your register settings with the ones attached. I had no problem getting an output with your settings. I had the NCO set to 1700MHz. I was getting a 0x0002 error for both 0x66 and 0x67, which is normal. After re-initializing the link and writing a 0x0000 to these registers to clear them, the errors went away.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

          Thanks for your timely reply,we test DAC38RF82 with your attached register settings;

    But,there is no data output;Sync always from High to Low.

    We read register  0x66 and 0x67;

    (1)register  0x66 is 0xc000;frame alignment errors;multiframe alignment error

    (2)register 0x67 is 0x4000; frame alignment errors.

     

    Could you give me some advices to solve these problems?

    Best Regards, 

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    If this is a custom board, what input pins on the DAC are you using for the 2 lanes? Is SYNC toggling or just staying low? Can you send your register settings?

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

          Thanks for your timely reply;

    (1)SYNC is toggling;screenshot as below

    (2)we use DAC_RX3 as JESD lane 0,DAC_RX2 as JESD lane 1

    (3) my register setting is attached as below

    22210_mod.cfg

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    Can you try using SYSREF in pulse mode and use 4 pulses? It appears the link is established for a period of time then goes down. Poor SYSREF timing could be an issue.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

          Thanks for your timely reply;

    (1)You means we generate sysref in pulse mode instead of continous mode?

    (2) Can I use the register 0x124 ''CDRVSER_SYSREF_DLY'' solve the problem?

    Regards,

    Wong

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

           I add some thing, we use all sysref  0x124=0x0010;0x15C=0x0001;sync is toggling;screenshot as below

    Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    Please change register 0x127 to 0x2222. All four blocks should use the same SYNC option. All other settings appear fine including 0x124 0x0010 and 0x15C 0x0001.

    Can you do the NCO only test to verify SYSREF is getting latched properly?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hello,Jim

       Today,we do the NCO only testting,we setted NCO freq =12MHz,We use an oscilloscope to check the output of the signal.

    but,We find a Puzzling problem.

    (1)In the mode LMFSHD=22210;We change register 0x127 to 0x1144;we use"sync_out from JESD" to sync NCO instead of sysref;but there is no data output

    (3) Some time ago,We tested in the mode LMFSHD=82121 ,we setted NCO freq =12MHz; we also set register 0x127 to 0x1144; Using "sync_out from JESD" to sync NCO ;DAC is working good;we can get NCO output 12MHz waveform

    We compare the two modes register setting,we can't find any discrepancy.

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    You must use SYSREF for syncing the NCO's for the NCO only test to be a valid. Why are you using sync_out from JESD? The NCO test does not have the link established and I think sync_out from JESD will not occur.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    Thanks for your Patient guidance

    (1)we set NCO=27MHz, SYSREF=10MHz; Changing register 0x127 to 0x2222.DAC use the sysref sync NCO;we also set bit 13 of register 0xC to a "0" in page 1 , 0x10C=0x0622;

    when we download firmware ,there is no data out;

    (2)We use FPGA DDS module generate DAC_RX data;There is a weird phenomenon;After we download firmware, we have to change the DAC_RX data frequency  one more time,then NCO can output data.In addition,DAC could output valid data only DAC_RX data frequency is 60MHz;others is either werid waveform or no output;

    we can set DAC_RX data frequency dynamically. The following operations are performed sequentially

    step one:DAC_RX data frequency=0MHz,firmware just download;DAC have no data output; Reading register  0x66 is 0x0000;0x67 is 0x0000; SYNC is OK

    step two:DAC_RX data frequency from 0MHz to 60MHz,DAC have no data output; Reading register  0x66 is 0x0000;0x67 is 0x0000

    step three:DAC_RX data frequency from 60MHz to 0MHz,DAC output NCO data,NCO is activated; ,FNCO=27MHz;Reading register  0x66 is 0x0000;0x67 is 0x0000

     

    step four:DAC_RX data frequency from 0MHz to 60MHz,DAC output 87MHz valid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step five:DAC_RX data frequency from 60MHz to 75MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step six:DAC_RX data frequency from 75MHz to 30 MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step seven:DAC_RX data frequency from 30MHz to 90MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step eight:DAC_RX data frequency from 90MHz to 20MHz,DAC no output  data;Reading register   0x66 is 0xC000;0x67 is Cx0000;ERROR occurs;SYNC is toggling

     


     


     


     

     

     

    step nine:DAC_RX data frequency from 20MHz to 10MHz,DAC no output  data;Reading register   0x66 is 0xC000;0x67 is 0xC000;ERROR occurs;SYNC is toggling

     


     


     


     

    step ten:DAC_RX data frequency from 10MHz to 0MHz,DAC  output  NCO frequency ;Reading register   0x66 is 0x0000;0x67 is 0x0000

     

     


     


     

     

     

    Best Regards,

    Wong

     

  • 0
    Prodigy 110 points

    If this is a custom board, what input pins on the DAC are you using for the 2 lanes? Is SYNC toggling or just staying low? Can you send your register settings?

  • 0 in reply to snow jhon
    Intellectual 570 points

    Hi,snow

          Thanks for your timely reply;

    (1)SYNC is toggling;screenshot as below

    (2)we use DAC_RX3 as JESD lane 0,DAC_RX2 as JESD lane 1

    (3) my register setting is attached as below

    0121.22210_mod.cfg

    Best Regards,

    Wong

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    Thanks for your Patient guidance

    (1)we set NCO=27MHz, SYSREF=10MHz; Changing register 0x127 to 0x2222.DAC use the sysref sync NCO;we also set bit 13 of register 0xC to a "0" in page 1 , 0x10C=0x0622;

    when we download firmware ,there is no data out;

    (2)We use FPGA DDS module generate DAC_RX data;There is a weird phenomenon;After we download firmware, we have to change the DAC_RX data frequency  one more time,then NCO can output data.In addition,DAC could output valid data only DAC_RX data frequency is 60MHz;others is either werid waveform or no output;

    we can set DAC_RX data frequency dynamically. The following operations are performed sequentially

    step one:DAC_RX data frequency=0MHz,firmware just download;DAC have no data output; Reading register  0x66 is 0x0000;0x67 is 0x0000; SYNC is OK

    step two:DAC_RX data frequency from 0MHz to 60MHz,DAC have no data output; Reading register  0x66 is 0x0000;0x67 is 0x0000

    step three:DAC_RX data frequency from 60MHz to 0MHz,DAC output NCO data,NCO is activated; ,FNCO=27MHz;Reading register  0x66 is 0x0000;0x67 is 0x0000

     

    step four:DAC_RX data frequency from 0MHz to 60MHz,DAC output 87MHz valid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step five:DAC_RX data frequency from 60MHz to 75MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step six:DAC_RX data frequency from 75MHz to 30 MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step seven:DAC_RX data frequency from 30MHz to 90MHz,DAC output  invalid data;Reading register  0x66 is 0x0000;0x67 is 0x0000

    step eight:DAC_RX data frequency from 90MHz to 20MHz,DAC no output  data;Reading register   0x66 is 0xC000;0x67 is Cx0000;ERROR occurs;SYNC is toggling

     

     

     

     

     

     

    step nine:DAC_RX data frequency from 20MHz to 10MHz,DAC no output  data;Reading register   0x66 is 0xC000;0x67 is 0xC000;ERROR occurs;SYNC is toggling

     

     

     

     

    step ten:DAC_RX data frequency from 10MHz to 0MHz,DAC  output  NCO frequency ;Reading register   0x66 is 0x0000;0x67 is 0x0000

     

     

     

     

     

     

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    DAC38RF82_Fs_5760_22210_mode.pptx1_I_Q_5760_2210_24x_K_24.cfgWong,

    Attached is a file showing the data captured from our system using your settings. I changed the RX_data from 1MHz to 10MHz then 60MHz without any issues. I think you may be having problems with your FPGA. How are the SYSREF and device clock generated in your system? This may be another issue to look into. The config file used is attached as well.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    Thanks for your timely reply;

    our clock tree is as below:

    (1) The chip HMC7044 generate reference clk and sysref to chip LMX2592 ,DAC38RF82, FPGA.

    (2)All output clocks of  Chip HMC7044 have the same phase .

    (3) HMC7044 Provide LMX2592_RefClk_120M to LMX2592 to generate synchronized clk Dev_Clk 7200M to DAC as DACCLK.

    (4) In my opinon , LMX2592_RefClk_120M and sysref_10M is synchronized, Dev_Clk 5760M is deterministic with the sysref_10M.

    Best Regards,

    Wong

  • 0 in reply to snow jhon
    TI__Guru* 91947 points

    Snow,

    What are these links? Why did you post this? A little information might help here.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hi Jim,

    Thanks for your help during these days,The reason is we misunderstand the frame format in the DAC38RF82 datasheet page 32;

    Our previous frame format is below

    Now we change the frame format as below

     


     

    Then we solved the problem.

     

    Finally,I want to say "Jim,Thank you very much!"

     

     

    Best Regards

     

    Wong

     

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

        I am sorry to bother you again;Not long ago, we thought the problem was solved. But recently discovered new problems when doing  further testing.

    Although DAC can output the correct waveform,But sometimes the sync is always toggling;

    For example:

    FPGA DDS module generate 100MHz baseband signal;NCO=12MHz;

    Result:

    (1)DAC output correct waveform 112MHz;

    (2)but,sync is always toggling

    (3)Reading 0x166 and 0x167 register;the value is 0xC000;it means"multiframe alignment error and frame alignment error "

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    I think the problem may be related to either the SYSREF timing or the RBD value may be to low. Can you try a larger value of K to allow you to use a large RBD value? Do you have any way of moving the SYSREF rising edge with respect to the DAC clock to change the setup and hold time?

    What happens if you turn off SYSREF after the link is established?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hi,Jim

    Thanks for timely reply,Today, I did the following test.

    1.I change K from 24 to 32,RBD=31;from 24 to 20,RBD=19;but, SYNC is still toggling

    2.I turn off SYSREF after the link is established,there is no effect on DAC output

    3.moving the SYSREF rising edge with respect to the DAC clock;some times ,DAC output  distortion signal

    sometimes,DAC output correct signal and the sync is toggling.

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    1.I change K from 24 to 32,RBD=31;from 24 to 20,RBD=19;but, SYNC is still toggling.

    Are you making these changes in the FPGA as well? Both the DAC and FPGA must have the same value for K.

    2.I turn off SYSREF after the link is established,there is no effect on DAC output.

    Is the DAC output valid? Is SYNC toggling in this case? Is toggling less or more?

    3.moving the SYSREF rising edge with respect to the DAC clock;some times ,DAC output  distortion signal sometimes ,DAC output correct signal and the sync is toggling.

    Can you run the NCO test per the attached document? There are a few other items in this document to help trouble-shoot your problem.

    Regards,

    Jim

    2287.Board trouble-shooting tips.docx

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    Thanks for your reply;

    1.Are you making these changes in the FPGA as well? Both the DAC and FPGA must have the same value for K?

     Yes,Both the DAC and FPGA  have the same value for K

    2.turn off SYSREF after the link is established,Is the DAC output valid? Is SYNC toggling in this case? Is toggling less or more?

    (1)Turn off SYSREF after the link is established,DAC output valid

    (2)SYNC is toggling in this case;

    Before turn off SYSREF;

    After turn off SYSREF;

    (3) I run the NCO test per your attached document,I find the sysref problem; set sysref=10Mhz,NCO=12MHz

    Set address 0x27 in page 1 and 2 to 0x2828 to use SYSREF as the SYNC source. SYSREF is present, But,the DAC output is a stable NCO tone;

    moving the SYSREF rising edge with respect to the DAC clock,But,the DAC output is still a stable NCO tone

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    Can you send your schematic? It appears you have an issue with the SYSREF timing. Is this signal AC or DC coupled?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    Here is our schematic

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    I need to see what is driving the SYSREF inputs and what standard these signals are driven as (LVPECL, LVDS, ect…).

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    the sysref is LVPECL  INPUT

    In addtion, the same custom board is working good In the mode LMFSHD=82121;SYSREF can reset NCO in many tunes;Sync  is not toggle

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    The SYSREF test is independent of the JESD interface. You should have failed this in both cases or passed it in both cases. Sync status is not irrelevant with this test.

    Ii appears from your schematics the interface is DC coupled. There is a good chance the SYSREF is not set to the correct common mode voltage of 0.5V. Can you check this on your board? You may want to replace R21 and R22 with 0.1uF capacitors to AC couple this interface and provide the proper common mode voltage.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    I am sorry to send you a picture less,The hardware engineer is confirmed that the SYSREF interface is AC coupled;

    Jim, I don't quite understand "run the DAC in NCO only mode",It means disable Rx ? Could you tell me in detail about the only NCO mode test?

    Best Regards,

    Wong

  • 0
    Intellectual 570 points

    Jim,

    I am a rookie in the workplace.I don't quite understand "run the DAC in NCO only mode" in "Board trouble-shooting tips",It need disable Rx ? Could you tell me in detail about the only NCO mode test?

    could you give me a detailed setting sequence?

    Thanks,

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    NCO_SYSREF_TEST_117MHz.cfgWong,

    After you configure the DAC for the 22210 mode, provide a dacclk = 5760MHz, and a SYSREF = 12MHz, load the DAC with the registers attached. After doing this, you should see many tones coming out of DACA if SYREF is continuously running. If this is true, next turn off SYSREF. You should now see only one tone out at 17MHz from DACA. If both of these tests pass, your DAC is receiving SYSREF properly.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hi Jim,

    I am very grateful for your patient guidance.

    1.we provide a dacclk = 5760MHz, and a continuously SYSREF = 12MHz, load the DAC with the registers your attached. After doing this, Seeing only one tone out at 17MHz from DACA.we try to adjust register 0x424 setting;sysref Centered on phase φ23 or Centered on phase φ34 or Centered on phase φ41;but it has no effect;

    2.Then we change a continuously SYSREF = 7.5MHz,many tones coming out of DACA.

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    Please operate with SYSREF at 10MHz and change your settings for the following registers:

    Add        Data

    0x40A    0xFC03

    0x124    0x0010

    0x15C   0x0001

    After making these changes, and establishing the link,clear registers 0x04 and 0x05 by writing a 0x0000 to them then both then read them back. Let me know what values you get for these.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

      Thanks for patient guidance,according to your advice; setting register 0x40A=0xFC03,0x124=0x0010,0x15C=0x0001

     clear registers 0x04 and 0x05 by writing a 0x0000 ;then  I read them back;0x04=0x00DB;0x05=0x013F

    settting sysref=10MHz,NCO=12MHz;Seeing only one tone out at 12MHz from DACA

    Best Regards,

    Wong

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    If you are using the same data input mapping as the TI board, in register 0x04, bits 2 and 3 should be "0". You are reporting a "1" in bit 3 which indicates you have no data coming in on RX3. I would double check the data coming out of the FPGA.

    For a possible SYSREF issue, try enabling the sysref alignment logic, by setting bit 0 of general configuration register 0x24 to a "1". When using this mode, you can make adjustments to the SYSREF timing using bits 13:12 and 15:14 of this same register. You can also monitor alignment statistics as well. See section 8.3.10 of the data sheet.

    Regards,

    Jim 

  • 0 in reply to Wong
    TI__Guru* 91947 points

    Wong,

    Are you still having issues with this?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 570 points

    Hi jim,

    I am on a business trip abroad,I am sorry that I failed to respond to you in time.

    I still puzzled with this problem When I left,two weeks ago; 

    Jim,I am very touched by your patient guidance and excellent professionalism.

    It will take me some days to go back.I will temporarily close this block;Once I go back, I will do the test as soon as possible.

    Best Regards,

    Wong

  • 0 in reply to jim s
    Intellectual 570 points

    Jim,

    I have already returned from a business trip.I have resolved this issue;Follow your  attached configuration,we offer pulse mode sysref to DAC,the issue is solved.

    Thanks for your your patient guidance and excellent professionalism.

    Best Regards,

    Wong