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ADC12D1600: Test Pattern

Amy Luo
Expert 6895 points
Part Number: ADC12D1600


Hi team,

Customers use PIN mode to control ADC12D1600, In Demux Mode, Non-DES Mode, power-on calibration, use test pattern, according to the datasheet description, test pattern will have a continuous 010. Now the data DI captured by customer in the FPGA FEF is two cycles, 010 is three cycles, and 010 does not appear twice the cycle of FEF. The timing constraints meet the requirements. What may be the problem?

Best Regards,
Amy Luo

  • 0
    TI__Mastermind 42200 points

    Hi Amy,

    The test pattern has been verified from the ADC and corresponds to the datasheet table 2.

    Is it possible for your test setup to capture the "Q" output test pattern instead? It would be interesting to see if the same issue is occurring.

    Where 008h should repeat two cycles on T4 & T5.

    Regards,

    Rob