ADC34J25: PRBS pattern

Hi Alexander,

In page 52 of the ADC34J25 datasheet (9.3.5.2), it says this in regard to the patter for PRBS.

"There are three different test patterns available in the transport layer of the JESD204B interface. The ADC34J2x supports a clock output, an encoded, and a PRBS (2^15 – 1) pattern. These patterns can be enabled via SPI register writes and are located in address 2Ah (bits 7:6)."

0Ah corresponds to channels A and B, while 0Bh corresponds to channels C and D. These registers should also work, but you should use register 2Ah to test the JESD interface with the PRBS pattern. I believe registers 0A and 0B are in place from the LVDS version of the chip (ADC3424) that does not require JESD testing, but still uses PRBS for LVDS interface testing.

Best Regards,

Dan

Hi Dan, thanks for your reply.

Still I have issues. I tried to use that test pattern in register 2Ah, and got this sequence (first 8 words):

e9e0; dee8; 6cdb; c072; 2b86; 53bf; 4329; 205c;

As I understand, the code to generate next word in sequence should be like this (Python):

a = 0xe9e0
for i in range(16):
    newbit = (((a >> 15) ^ (a >> 14)) & 1)
    a = ((a << 1) | newbit) & 0xffff

But the produced sequence does not look like what I got. Is my algorithm wrong?

Here I found reference algorithm and sequence, and it also does not look like what I got from ADC:

https://blog.kurttomlinson.com/posts/prbs-pseudo-random-binary-sequence

The data from ADC is right, every other test pattern works good.

Best Regards,

Alexander Orlov