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ADS54J64: Settings for TEST Pattern (Register 91h)

Part Number: ADS54J64

I'm debugging my designed ADS65J64 board with original Xilinx FPGA(XC7K160T-2FFG676C)

board.

Now, I make sure that JESD204B is running correctly. 

ADC mode 8 (DDC Bypass mode).

There is a problem that I don't get ADC test pattern, correctly.

TestPattern mode 1,2,6 are running. I can get correct data.

However, mode 3(toggle), 4(ramp),7,8(custom)  are NG as below.

mode3 : AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA

(always all "A")

mode4: 0000 0000 0000 0000 0000 0000 0000 0000

(alwasy all "0")

Pls teach me how to set registers for test pattern.

*** ADC settings

# ----------------
# Hardware reset
# 1ms puls
RESET();

# ----------------
# Pulse a reset (low to high to low) via a hardware reset (pin 48), wait 100 μs
sleep( 0.1 );

# ----------------
# Issue a software reset to initialize the registers
#
RegWrite( 0x0000, 0x81 );
RegWrite( 0x0000, 0x80 );

# ----------------
# Set the high SNR mode for channel pairs AB and CD, select
# trims for 500-MSPS operation
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x01 );
RegWrite( 0x0013, 0x00 );
RegWrite( 0x00AB, 0x01 );
RegWrite( 0x00AC, 0x01 );
RegWrite( 0x00AD, 0x08 );
RegWrite( 0x00AE, 0x08 );
RegWrite( 0x0064, 0x02 );

# ----------------
# Set up the SerDes configuration
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x60 );
RegWrite( 0x0013, 0x00 );
RegWrite( 0x0025, 0x80 );
RegWrite( 0x0026, 0x0F );
RegWrite( 0x0020, 0x80 );

# ----------------
# ADC calibration
RegWrite( 0x0011, 0xFF );
RegWrite( 0x0012, 0x00 );
RegWrite( 0x0013, 0x00 );
RegWrite( 0x00D5, 0x08 );
time.sleep( 0.005 );
RegWrite( 0x00D5, 0x00 );
RegWrite( 0x002A, 0x00 );
RegWrite( 0x00CF, 0x50 );

# ----------------
# Select trims for the second Nyquist
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x1E );
RegWrite( 0x0013, 0x00 );
RegWrite( 0x002D, 0x02 );

# ----------------
# Load linearity trims
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x01 );
RegWrite( 0x0013, 0x00 );
RegWrite( 0x008C, 0x02 );
RegWrite( 0x00B7, 0x01 );
RegWrite( 0x00B7, 0x00 );

# ----------------
# Disable SYSREF
#
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x00 );
RegWrite( 0x0013, 0x01 );

RegWrite( 0x006F, 0x40 );
RegWrite( 0x006A, 0x02 );

# ----------------
# For debug
# Settings TEST Pattern
#
RegWrite( 0x0011, 0x00 );
RegWrite( 0x0012, 0x01 );
RegWrite( 0x0013, 0x00 );

# Custom Pattern 1
RegWrite( 0x008E, 0xC3 ); # 15:8
RegWrite( 0x008D, 0x96 ); # 7:0

# Custom Pattern 2
RegWrite( 0x0090, 0x5A ); # 15:8
RegWrite( 0x008F, 0xA5 ); # 7:0


# Activate Test Pattern mode
RegWrite( 0x0091, 0x64F );

*** Result of registers readback

---- ADS54J64 DUMP ----
---- DIGTOP PAGE ----
0064h : 02
008Dh : 96
008Eh : C3
008Fh : A5
0090h : 5A
0091h : 4F
00A5h : 00
00A6h : 00
00ABh : 01
00ACh : 01
00ADh : 08
00AEh : 08
00B7h : 00
008Ch : 02
---- ANALOG PAGE ----
006Ah : 02
006Fh : 40
0071h : 00
0072h : 00
0093h : 00
0094h : 00
009Bh : 00
009Dh : 00
009Eh : 00
009Fh : 00
00AFh : 00
---- SERDESXX PAGE ----
0020h : 80
0021h : 01
0022h : 00
0023h : 00
0025h : 80
0026h : 0F
0028h : 00
0036h : 01
0041h : 00
0042h : 00
---- CHX PAGE ----
0026h : 00
0027h : FF
002Dh : F0
0078h : FF
007Ah : FF
007Bh : FF
007Eh : 0F
---- ADCXX PAGE ----
0007h : 02
0008h : 00
00D5h : 00
002Ah : 00
00CFh : 50
--------------------