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Which JESD204B lines should be length matched?

canberk unal
Prodigy 150 points
Other Parts Discussed in Thread: ADS42JB46, DAC38J84, LMK04828

Hi everyone, 

I am designing a ADC/DAC pcb which includes two ADS42JB46, and one DAC38J84. I have few questions. 

1- DAC's RX lines doesn't have to be length matched I guess? (Of course two differential lines should be length matched)

2- Likewise ADC's TX lines doesn't have to be length matched, am I correct? 

3- ADC's SYSREF and CLKIN should be length matched right? But I don't know if all ADC1's ADC2's and DAC's SYSREF and CLKIN should be length matched? 

4- I don't know if SYNC lines should be length matched to other differential line? 

Thanks in advance. 

Canberk 

  • 0
    TI__Genius 12780 points

    Hi Canberk,

    We are taking a closer look into your question, and will be back with you soon.

    Best Regards,

    Dan

  • 0
    TI__Guru* 91947 points

    Canberk,

    1- DAC's RX lines doesn't have to be length matched I guess? (Of course two differential lines should be length matched)

    Correct.

    2- Likewise ADC's TX lines doesn't have to be length matched, am I correct? 

    Correct.

    3- ADC's SYSREF and CLKIN should be length matched right? But I don't know if all ADC1's ADC2's and DAC's SYSREF and CLKIN should be length matched? 

    All of the ADC's and DAC's SYSREF and CLKIN need to match each other for deterministic latency.   

    4- I don't know if SYNC lines should be length matched to other differential line? 

    If using Subclass 1, the SYNC's do not have to be matched to anything. If using Subclass 0 or 2, the SYNC's must be matched length in most cases along with a other timing requirements.

    Regards,

    Jim  

  • 0 in reply to jim s
    Prodigy 150 points

    Thank you very much Jim, 

    About question-3, I didn't understand completely, for example ADC1's SYSREF and CLKIN need to be length matched, that's ok, but also need to be length matched DAC's SYSREF-CLKIN and ADC2's SYSREF and CLKIN lines, correct? 

    Regards, 

    Canberk 

  • 0 in reply to canberk unal
    TI__Guru* 91947 points

    Canberk,

    If you want to have your ADC's to be synchronized and have deterministic latency, the SYSREF and device clock need to be matched for all ADC's. Same goes for the DAC's. The ADC SYSREF and device clock do not need to match the DAC ones though. Same goes for the SYSREF and device clock going to the FPGA or ASIC. They need to be matched by they do not need to match the length of the ADC or DAC.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 150 points

    Thank you very much Jim, that's very helpful. 

  • 0 in reply to jim s
    Prodigy 150 points

    Dear Jim, 

    I have one last question. Are the reference clocks for the gigabit lanes must be length matched? (GBTCLK-1 and GBTCLK-2) By the way, I am using LMK04828 for clock generation and FPGA.

    Can LMK04828's programmable digital delay be used for outputs' signal synchronization. 

    Best Regards, 

    Canberk 

  • 0 in reply to canberk unal
    TI__Guru* 91947 points

    Canberk,

    These should be matched and they should be matched to the SYSREF pair going to the FPGA.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 150 points

    Jim, 

    As you said earlier, reference clock and SYSREF for FPGA logic must be matched. Should I also match  GBT (or GBT) Clock(for FPGA's MGTs) signals to them? 

    Regards, 

    Canberk 

  • 0 in reply to canberk unal
    TI__Guru* 91947 points

    Yes. The reference clock I was referring to was the MGT clock.

  • 0 in reply to jim s
    Prodigy 150 points

    Jim thank you very much for answering my questions. 

    I am little confused because of the ADS42JB46's evaluation kit design. 

    There are JESD core clock , JESD core SYSREF, and then GTX CLK. IF GTX_CLKP/N is used for the reference clocks for the gigabit lanes, then what are others for? Also I have seen other designs which use two GTX_CLK signals, which I am trying to ask if they should be matched to each other? 

    Regards, 

    Canberk

  • 0 in reply to canberk unal
    TI__Guru* 91947 points

    Canberk,

    When the JESD204B standard first came out, Xilinx created firmware for TI to interface Xilinx FPGA development boards with our JESD204B boards. This early firmware used both a core clock and reference clock. Using a separate clock for the core clock is not required. The TSW14J56EVM, which uses an Alter FPGA, does not use a core clock. I am not sure what firmware or FPGA you are using but I am guessing you do not need the core clock. If you plan on using more then one reference clock (GTX_CLK) I would make these matched length. In most cases, you should only need one of these clocks.

    Regards,

    Jim