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Original question:

Occasional extra DRDY pulses from ADS1675

ADS1675: ADS1675 DRDY spike

myNickname
Prodigy 70 points
Part Number: ADS1675

Hello Keith,

I am observing an undocumented behavior of ADS1675. There is sometimes a spike on DRDY near the second falling edge of CLK after applying START. The duration of the spike is approx. 1/3 of Tclk. The length of a real DRDY is Tclk. My settings: DRATE = 101, High-Speed LVDS. CLK Signal is continuously driven by a PLL. These seem to be the same spikes or pulses that Sascha Langener reported back in 2014 “Occasional extra DRDY pulses from ADS1675”.

Regards.

  • 0
    TI__Mastermind 39070 points

    Hello,

    As you pointed out, it does appear other customers have seen similar behavior.  Could you provide a few more details to help track down why you are seeing this glitch?

    1.  What CLK frequency are you using?

    2.  What is the magnitude of the CLK signal?  (It should be 5Vpp, referred to the analog supply.)

    3.  Is the START signal the first START after power-up, or a low/high speed mode change, or change in the CLK frequency?

    If the CLK changes frequency enough to cause the PLL to lose lock, it will require additional time to re-lock, which would then pulse the DRDY line.  

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 70 points

    Hello Keith,

    1) The frequency of CLK is 32 MHz.

    2) Scales of channels in the picture are green=5V, pink=2V, purple=2V and time base is 20 ns.

    3) START signal is not the first START after power-up. No changes have been made to CLK frequency or mode.

    I removed probe from CLK signal to not degrade it and checked again. The pulses still occurred, maybe one in ten starts.

    Regards.

  • 0 in reply to myNickname
    TI__Mastermind 39070 points

    Hello,

    I need to do some additional research on this matter.  For now, if possible, I suggest ignoring any /DRDY activity near the START edge, as suggested by another customer.

    I will follow-up early next week.

    Thank you.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    TI__Mastermind 39070 points

    Hello,

    How long is START low before the rising edge?

    A possible cause of the 'glitch' on DRDY may be due to the START rising edge occurring a few clocks before a previous conversion DRDY is issued.  There is some delay from the rising edge of START before the RESET process starts.

    I checked the operation of the START and DRDY on the ADS1675REF evaluation board, and the START pin is held low for several uS before going high.  I looked at several instances of the START pin transition, and did not see any glitches on the DRDY pin.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 70 points

    Hello Keith,

    START is low for several milliseconds before rising edge. In the attached picture START is low for more than 900 microseconds.

    I do not follow your thesis. I guess the pulse is either caused by something analog like the LVDS driver circuit powering up or something digital like synchronization or race condition with SCLK.

    The pulse most of times is one SCLK cycle in width (see picture).

    Regards.