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ADS131A02: Clock source

Y.Ottey
Mastermind 6145 points
Part Number: ADS131A02
Other Parts Discussed in Thread: ADS131A04

Dear all 

I would like to ask questions about clock source of ADS131A02.

1. According to Datasheet, the typical value of fCLKIN is 16.384MHz.

If a frequency larger than this value (for example, 20 MHz) is input, the conversion time is considered to be shortened.

Are there any other effects other than conversion time?

(Please let me know if there are any disadvantages when increasing the frequency.)

２．The data sheet shows that SPI SCLK can also be used as an external input clock. Furthermore, the frequency is in the same value range as fCLKIN. I think using SCLK is fine, but are there any disadvantages compared to using fCLKIN?

(If SCLK is used, if there are restrictions other than frequency, please let me know.)

Best Regards,

Y.Ottey

  • 0
    TI__Guru* 99405 points

    Hi,


    1. There shouldn't be significant changes in the operation going from a ~16MHz clock to a 25MHz clock. I did notice this previous post on the question:

    e2e.ti.com/.../573251

    Based on my experience with these data converters, I would agree with the comments in that post. By changing the clock rate for the ADC, you may have some minor changes in the performance. You might have a small change in the INL performance or the gain error, but I would guess these changes would be smaller than the maximum specifications. In the cases I've seen, the specification changes for changes in the master clock occur when the clock changes, by factors or two or four. Going from 16.384MHz, to 20MHz is a rather small change in the clock frequency.

    2. I don't think there is any difference in performance using the SPI CLK as the external input clock. The clock input is conditioned enough that it should be the same regardless of clock source.



    Joseph Wu

  • 0 in reply to Joseph Wu
    Mastermind 6145 points

    Dear Joseph

    Thank you for your reply.

    I would like to ask about your answer.

    You gave me the following answer:

    In the cases I've seen, the specification changes for changes in the master clock occur when the clock changes, by factors or two or four. Going from 16.384MHz, to 20MHz is a rather small change in the clock frequency.

    What does the factor in this answer mean?

    I would be happy if you could explain this in detail.

    Regards,

    Y.Ottey

  • 0 in reply to Y.Ottey
    TI__Guru* 99405 points

    Y.Ottey,


    I've made some measurements before on other devices, playing with the master clock frequency. In one device, we set specifications with a 2MHz clock. Looking at the performance, as I changed the master clock from 2MHz, 4MHz, 6MHz, to 8MHz, I could see the INL go from 3ppm to about 8ppm (the biggest shift in the upper two frequencies). There were some minor changes in gain error (probably about 0.01% change from 2MHz to 8MHz). There was also a change in offset of about 10uV, but I didn't try to calibrate offset before running the test.

    I don't have any similar measurements for the ADS131A04 over different clock frequencies. However, I do think that a change in clock frequency from 16MHz to 20MHz won't have substantial change in operation.


    Joseph Wu