AFE58JD32: odd input and even input

16 ADCs are used to convert the 32 inputs. Each ADC converts one odd numbered input (processed in the VCAo die) and one even numbered input (processed in the VCAe die) in a time multiplexed manner. I know we can splits the ADC output data stream into the odd and even number channels  through rising edges and falling edges of FCLK in LVDS mode. But what shoud we do to splits the ADC output data stream into the odd and even number channels in JESD204B mode?