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DAC5675-EP: lowering Clk speed and reducing power consumption?

AnBer
Mastermind 29340 points
Part Number: DAC5675-EP
Other Parts Discussed in Thread: DAC5675

Team,

Looking at the DAC5675-EP datasheet - SGLS381A page 7:
-Only typical Clock pulse width (tw(H)/Tw(L)) are given.
Can the DAC operate with a CLK speed as low as 1Mhz?
What would be the drawback to operate at this speed?
Are there some specfic design guidelines to follow to operate at this CLK speed?

-Do we have power consumption figures for Clock speed of 1Mhz?
How can be the power consumption approximated for 1Mhz?
Are there some specific design guidelines to follow to reduce as much as possible the power consumption of the DAC5675?

Thanks in advance!

A.

  • 0
    TI__Genius 14540 points

    The datasheet spec table only provides specs for clock speeds as low as 100 MHz, and these are typical values only.  This means these values were derived from a statistical characterization during the release of this device. Since no information is provided in the datasheet at clock speeds lower than 100MHz, I can only speculate no data exists.  I will see if I can locate the original characterization data to confirm but most likely we will not be able to provide much information operating the device at 1MHz speed.

    Thanks

    Christian

  • 0 in reply to Christian Yots
    TI__Mastermind 29340 points

    Hi Christian,

    -Were you able to find more information from characterization?

    -Do we have some other device in -EP that would be close to the DAC5675 specs but for 1 Mhz and with as low power as possible?

    Thanks in advance,

    A.

  • 0 in reply to AnBer
    TI__Genius 14540 points

    I was not able to find any more characterization data.  I am reassigning  your request to the team that developed this device to ask if they have any additional information.

    Thanks

    Christian