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AFE5401-Q1: DSYNC1-HIGH and DSYNC2-LOW ?

cyan zhou
Expert 1500 points

Part Number: AFE5401-Q1

customer use AFE5401-Q1 , in datasheet Figure.78 as below:

What is the mean of DSYNC1-HIGH and DSYNC2-LOW? How to configure？ How to configure the Register 1A 1B ?

  • 0
    TI__Guru 50036 points

    Hi Cyan,

    I am checking with my team on the details of DSYNC1_HIGH and DSYNC2_LOW.

    In the meantime, I have a few questions related to your customer. Can I send you a message to the email registered at ti.com?

  • 0 in reply to Praveen Aroul
    Expert 1500 points

    Could please give me your mail, I'll write mail to you and loop customer, thanks！

  • 0 in reply to cyan zhou
    TI__Guru 50036 points

    Hi Cyan,

    Please send the email to the mailing list: afe5401_info@list.ti.com

  • 0 in reply to Praveen Aroul
    Expert 1500 points

    My Colleague already sent the mail on 11.1，but still no reply till now.

  • 0 in reply to cyan zhou
    TI__Guru 50036 points

    Hi Cyan,

    Please check the email for my response.

    Response posted here for the benefit of other users.

    DSYNC1_HIGH (reg. 0x1B) refers to the extra time (in terms of tAFE_CLK cycles) in addition to the 50% pulse high duration of DSYNC1 during the COMP_DSYNC1 period.

    The total time DSYNC1 would be high is defined by the equation: high for [(DSYNC1_HIGH + COMP_DSYNC1 ÷ 2) Mod COMP_DSYNC1]

    For example, let us say COMP_DSYNC1 = 10, DSYNC1_HIGH = 0, then DSYNC1 will be high for 5 AFE_CLK cycles.

    If DSYNC1_HIGH = 1, then DSYNC1 will be high for 6 AFE_CLK cycles and so on.

    Similarly, DSYNC2_LOW is defined as the low pulse duration during the Sample Phase. DSYNC2_LOW is defined in registers 0x19 and 0x1A.

    For example, let us say if SAMPLE_COUNT = 9 and DSYNC2_LOW = 2, then during the SAMPLE PHASE, DSYNC2 will be high for 8 AFE_CLK cycles and low for 2 AFE_CLK cycles.