ADS5263: problems with synchronization

Val Valeriy

Part Number: ADS5263

Hello folks. I have a problems with synchronization ads5263. I have device with ADC ads5263 and FPGA Cyclone V. For synchronization i use frame clock (ADCLK). At 100 MHz input ADC clock (clkp/clkn), device not sinhronize at temperature -5 celcius degrees. But if i reduce input ADC clock (clkp/clkn) to 98 MHz device is sinhronize.
What can it be?

Best regards, Val.

over 6 years ago

0 Xiaochen (Sean)Xu over 6 years ago

TI__Expert 6040 points

Val,

Thanks for using TI device! Typically LVDS timing tuning is required when temperatuer changes. from room temp to -5C, you need run another DPA to lock LVDS.

at 98MHz, the speed is slower, so you can lock in. this indicates that the timing delay is slightly shifted at -5C.

you may reach Altera team and see if they have DPA detaisl for temperature tuning.

Thanks!

0 Val Valeriy over 6 years ago in reply to Xiaochen (Sean)Xu

Intellectual 430 points

Thanks!

Data converters

Data converters forum

ADS5263: problems with synchronization