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ADS54J60: Pins of Power down, Overrange indication and Data outputs

Jason(qx) Wang
Intellectual 500 points
Part Number: ADS54J60


Hi, Dear Supports: I have questions below.

Q1: For power down pin PDN (pin 50), does it actually have a internal 20K pulled down to Ground?

Q2: To set device power down by hardware, pull down PWN pin to Ground or pull up it to DVDD?

Q3: The datasheet says pin SEN is pulled up to IOVDD with 20K internally, is this incorrect, the correct is to DVDD?

Q4: For pins of PDN, RESET, SCLK, SDIN, SEN, SDOUT, SYNCB, their power supply is DVDD?

Q5: Pin PDN and SDOUT can also be as indications of Fast-Over-Range, the indication signals are internally latched or unlatched? Because, if they are unlatched, and I want to see by LEDs, I need external lathers.

Q6: For JESD204B data outputs (D[A,B][0:3][P,M}, total 8 pairs), they work in AC couple with a serial 0.1uF each line. In my circuit, the receiver is FPGA, in the PCB layout, these serial 0.1uF capacitors should be placed close to ADS54J60 side, or close to FPGA side, especially when ADS54J60 and the FPGA are in different boards (connected by connector)?

Q7: Also for JESD204B data outputs (D[A,B][0:3][P,M}, total 8 pairs), datasheet page 83 shows, 100 ohm termination per pair.  Should place these 100 ohm before serial 0.1uF (on ADC chip side), or after serial 0.1uF (on FPGA side)?

  • 0
    TI__Guru* 91947 points

    Jason,

    Q1: For power down pin PDN (pin 50), does it actually have a internal 20K pulled down to Ground? Yes.

    Q2: To set device power down by hardware, pull down PWN pin to Ground or pull up it to DVDD? Pull up to DVDD.

    Q3: The datasheet says pin SEN is pulled up to IOVDD with 20K internally, is this incorrect, the correct is to DVDD? It should say "DVD".

    Q4: For pins of PDN, RESET, SCLK, SDIN, SEN, SDOUT, SYNCB, their power supply is DVDD? Yes for all of these.

    Q5: Pin PDN and SDOUT can also be as indications of Fast-Over-Range, the indication signals are internally latched or unlatched? Because, if they are unlatched, and I want to see by LEDs, I need external lathers. I am looking into this but to be on the safe side, you may want to add a transistor to drive the LED.   

    Q6: For JESD204B data outputs (D[A,B][0:3][P,M}, total 8 pairs), they work in AC couple with a serial 0.1uF each line. In my circuit, the receiver is FPGA, in the PCB layout, these serial 0.1uF capacitors should be placed close to ADS54J60 side, or close to FPGA side, especially when ADS54J60 and the FPGA are in different boards (connected by connector)? The cap placement is not critical.

    Q7: Also for JESD204B data outputs (D[A,B][0:3][P,M}, total 8 pairs), datasheet page 83 shows, 100 ohm termination per pair.  Should place these 100 ohm before serial 0.1uF (on ADC chip side), or after serial 0.1uF (on FPGA side)? The FPGA should have 100 Ohm internal termination. If it does not, place these on the FPGA side after the caps and as close as possible to the FPGA.

    Regards,

    Jim 

  • 0
    Intellectual 500 points

    Hi, Dear Supports:

    For ADS54J60,  pin PDN and SDOUT, when  they used for Over-Range indications:

    Q1: What active level they are, active High or active Low?

    Q2: I have not gotten the answer that the indication signals are internally latched or unlatched? 

    Thank you very much,

    Jason

  • 0 in reply to Jason(qx) Wang
    TI__Guru* 91947 points

    Jason,

    The OVR is active high when using the PDN or SDOUT pins. I am waiting to here from design regarding your other question.

    Regards,

    Jim