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ADS1278: ENOB and SNR in the case of a signal with an amplitude of 20 dB below the FSR.

Fabio Soriano
Expert 4080 points
Part Number: ADS1278

Hi team,

I received the following request from a customer I'm following. Could you assist?

###################################################################

The component will be used in HIGH SPEED mode with a fCLK of about 34 MHz with a VREF of 2.048V.

We want to calculate ENOB and SNR in the case of a signal with an amplitude of 20 dB below the FSR.

From page 6 of the datasheet I have the value of SNR and THD, but in the conditions described above (ie fclk = 27 MHz, VREFP = 2.5V): therefore the value of SNR and ENOB will be less than what I can calculate, since my fCLK (and therefore the sampling rate) are higher.

At a signal with -20dBFS, how much will these values be? I don't seem to have found details that allow me to calculate these quantities.

You can help me?

####################################################################

Regards,

Fabio

  • 0
    TI__Mastermind 46360 points

    Hi Fabio,

    For the ADS1278, the noise with shorted inputs closely predicts the resulting SNR.  Figure 46 in the datasheet shows how noise and THD change with respect to the CLK frequency.

    Noise is about the same, and THD increases by about 3dB.  With Vref=2.048 and Fclk=34MHz, I estimate SNR and THD to be around:

     

    -0.5dBFS INPUT (0.944)

    SNR = 20*log[(0.944*2.048/1.414)/(8.5/1000000)] = 104dB (full scale input)

    THD = -108dB + 3dB (fclk=34MHz) = -105dB

    SINAD = -20*log[SQRT(10^(-SNR/10) + 10^(THD/10))] = 101.5dB

    ENOB = ( SINAD- 1.76)/6.02 = 16.6b

    -20dBFS INPUT (0.1)

    SNR = 20*log[(0.1*2.048/1.414)/(8.5/1000000)] = 84.6dB (full scale input)

    THD = -125dB + 3dB (fclk=34MHz) = -122dB (per figure 18)

    SINAD = -20*log[SQRT(10^(-SNR/10) + 10^(THD/10))] = 84.6dB

    ENOB = ( SINAD- 1.76)/6.02 = 13.8b

    For more information on the above equations I used, please refer to the ADC section (page 130 in the 5th addition) in the Analog Engineer's Pocket Reference guide.

    http://www.ti.com/tool/ANALOGPRGBK

    Of course, the above calculations are estimates.  I will take some measurements on the EVM and provide those by next Monday.

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Expert 4080 points

    Thanks Keith,

    Let me know once you have verified it with some measure.

    Regards,

    Fabio

  • 0 in reply to Fabio Soriano
    TI__Expert 4080 points

    Hi Keith,

    Could you share the same graph representing Total Harmonic Distortion and Noise vs Clk in the -20dBFS case?
    In addition, you might know what the max THD is in the -20dBFS case?

    Regards,

    Fabio

  • 0 in reply to Fabio Soriano
    TI__Mastermind 46360 points

    Hi Fabio,

    I am collecting measurements and will post the results tomorrow.  For your latest question, I only have access to the EVM, and it does not easily allow adjustment of the CLK input.

    Thanks,
    Keith

  • 0 in reply to Keith Nicholas
    TI__Mastermind 46360 points

    Hi Fabio,

    I collected data on the EVM under the following conditions:

    Fclk=32.768MHz (maximum supported on the EVM)

    Vref=2.048V

    -0.5dBFS INPUT (0.944)


    SNR=102.6dB

    THD=-106.0dB

    SINAD=101.0dB

    -20dBFS INPUT (0.1)

    SNR=84.2dB

    THD=-100.0dB

    SINAD=84.1dB

    I still need to do some more digging, but I do not think we have THD and Noise data plots verses CLK for the -20dBFS case.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    TI__Expert 4080 points

    Hi Keith,

    I received a new request:

    ######################

    Figure 84 of the datasheet shows a power sequencing, of which however I cannot find the data inside the document itself; how much time must pass between the start of a supply and the others? Is this sequence mandatory?

    ######################

    Regards,

    Fabio

  • 0 in reply to Fabio Soriano
    TI__Mastermind 46360 points

    Hello Fabio,

    The power supply sequence is needed to insure the internal power-on reset works properly.  However, you do not need to meet any specific power-up sequence for reliable operation as long as you assert the /SYNC pin after all power supplies have settled to within recommended operating voltages and after the first data appear.

    Regards,
    Keith