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ADS1256: ADC output is not correct for 100Hz and above analog sine input frequency

Rashmi Mhapsekar
Prodigy 70 points
Part Number: ADS1256

Hi,

I am working on ADS1256.

Firmware is in Python which is taken from github. Using PiPyADC - Python module for interfacing SPI bus based analog-to-digital converters with the Raspberry Pi.

In firmware, Analog signal is read using read_continuous method.

The settings as follows:

Data rate = 2Ksps

PGA = 1

Input buffer is off.

Clock frequency = 7.86Mhz.

I am using ADC channel0 for analog input.

Analog input is sine wave which is having frequency 1Hz, 10Hz, 100Hz, 1KHZ.

For 1 and 10Hz ,  I am getting correct output frequency 1 and 10Hz.

The issue is not getting output for 100Hz onwards.

Please help me on resolving the above mentioned issue.

Thanks,

Rashmi

  • 0
    TI__Mastermind 44680 points

    Hi Rashmi,

    Welcome to the TI E2E Forums!

    When you say, "The issue is not getting output for 100Hz onwards", do you mean that you are not seeing any data at all, or that you are seeing incorrect data?

    I know the ADS1256's digital filter will slightly attenuate 100 Hz signals (by about -0.1 dB) at the 2 kSPS data rate, but I'd still expect to see a sine wave on the output.

    I've heard of others having issues using some Python-based SPI software libraries for communicating with the ADS1256 on the Raspberry Pi (https://e2e.ti.com/support/data-converters/f/73/p/475295/1788391). The issue was that some of these libraries were not fast enough to capture the data from the ADC when the ADS1256 as configured for some of the higher data rates.

    You might consider connecting an oscilloscope or logic analyzer to the SPI pins and "/DRDY" to see if the RasPi is able to keep up with the ADC and capture the data with every /DRDY falling edge.

    Another thing to look out for is when data is captured. In continuous capture mode, the data needs to be read well in advance of the next /DRDY falling edge. The ADC data is shifted out of a register that gets updated around the time that /DRDY goes low. Therefore, if you are reading data DURING a /DRDY falling edge, then the data will be corrupted (i.e. it will be a mixture of the old and new conversion data). Ideally, data should get clocked out immediately (or at least consistently soon) after the /DRDY falling edge. If you see that data is clocked out at varying times after the /DRDY falling edge, it may be a sign that the microcontroller is not keeping up with the ADC's output data rate. 

    Let me know that helps!

  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Hi Chris,

    Thanks for your response.

    I am getting sine wave at ADC output (checked it by plotting in excel) for 100Hz analog input signal.

    The problem is not getting more samples for each cycle at input frequency 250Hz, 500Hz and 1KHz.

    Basically there are ADC data conversion and data reading from MCU time.

    Even though , sample rate changed to 3750 sps, I am not getting more samples for each cycle and not correct sine wave.

    So data reading over SPI to MCU adds delay. Please confirm.

    Currently SPI frequency is 976563Hz.

    Is it safe to change to 1953125Hz.

    Or Any other option to speed up data reading process.

    Thanks in advance.

  • 0 in reply to Rashmi Mhapsekar
    TI__Mastermind 44680 points

    Hi Rashmi,

    I would recommend looking at the /DRDY and SPI signals on an oscilloscope to check for two things:

    1. By increasing the ADC's data rate, you should see the time between /DRDY falling edges decrease. The time between /DRDY falling edges should correlate with the period of the selected output data rate.

    2. Look the SPI communication to see if your MCU is reading data as the same rate as the ADC is producing conversion results. It's possible the MCU is reading data as fast as it can and increasing the ADC's data rate is not not providing you with any additional data because the MCU is not able to keep up.

    The ADS1256 SCLK can be up to 1/4th the frequency of the ADC's master clock. Therefore, if you're using the nominal 7.68 MHz master clock, then the SCLK can go as fast as 1.92 MHz. Running SCLK at its maximum frequency can help to reduce the amount of time it takes the MCU to clock out the conversion result.

  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Hi Chris,

    Thanks for your valuable response.

    I will check DRDY signal.

    I have configured data rate to 30000 sps in my code.

    And I am reading ADC data in continuous mode.

    When I ran the script, I got 10000 samples per sec only .

    Could you please explain the reason and what shoud I do to resolve it.

    My another question is I am reading data over two channels using sequence method.

    My observation is for 2000sps, I received around 500 samples per sec for each channel.

    Could you please explain the reason and what shoud I do to resolve it.

    Thanks in advance.

    Rashmi

  • 0 in reply to Rashmi Mhapsekar
    TI__Mastermind 44680 points

    Hi Rashmi,

    For the 30 kSPS data rate are you multiplexing between channels, or are you only getting 10 kSPS while continuously converting?

    The ADS1256's digital filter is a kind of moving average filter that requires multiple samples in order to compute the average. The first conversion result always takes longer to compute, but from then on you get data out at the expected data rate. However, when you multiplex between channels, this moving average filter has to be cleared and then recalculate a new first result on the second channel.

    Take a look at tables 13 and 14 in the datasheet to get an idea of the maximum data throughput you can achieve while multiplexing.

  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Hi Chris,

    Thanks for response.

    For 30KSPS , I am reading in continuous mode and not doing multiplexing. The output is only getting 10KSPS.

    Table 15 shows setting time (DRDY period) is 5 for 30KSPS.

    Is this the reason I am getting 10KSPS? Please confirm.

    Thanks 

  • 0 in reply to Rashmi Mhapsekar
    TI__Mastermind 44680 points

    Hi Rashmi,

    If you're measuring a single ADC channel continuously (not multiplexing), then you should be getting the expected output data rate. However, the output data rates of the ADS1256 do depend on the crystal/clock frequency. The 30 kSPS data rate assumes you're providing a 7.68 MHz clock. However, if you were to use a slower clock frequency then the ADC's output data rate would scale proportionally. Therefore, 10 kSPS would be the expected output data rate if you programmed the ADS1256 for 30 kSPS but only clocked it with a 2.56 MHz clock.

    The settling time/MUX latency only has to do with the first ADC conversion result. Each time you switch channels or restart a conversion, the first result will take up to 5 time longer than the on-going data rate.

  • 0 in reply to Christopher Hall
    Prodigy 70 points

    Hi Chris,

    Thanks for your valuable response.

    Today, I checked DRDY pin status. And I found that MCU is not able to keep with DRDY pin. I think this is the reason we are getting around 10K samples for 30K

    sampling rate.

    I am using High-Precision AD/DA board with the Raspberry Pi using Python module. 

    Could you please recommend any other suggestion to resolve it.

    Thanks in advance.