Part Number: ADS54J69
Other Parts Discussed in Thread: DXP,
I am new to ADC design and JESD204B interface and using "Xilinx ultrascale+ FPGA" to interface ADC from GTH bank side. Below are few points which is not clear to me and requested to clarfy.
1. As per ADS54J69 Datasheet, "on page no.11" for "JESD204B Interface: DxP, DxM", "Vod=700mVpp & Voc= 450mV" typical. As per Xilinx "DS 925" on "page no. 79" for "GTH Transceiver DC Specifications", "DVppin =150 - 1250mV & Vcmin= 2/3 Vmgtavtt" i.e 800mV (Vmgtavtt" =1.2V). Will this interface works if connecting "DxP & DxM" pin to Xilinx "GTH transceiver rx input" pins?
2. As per ADS54J69 Datasheet, "on page no.13, figure 2" its seems that for every clock one sample is taken. In this point of view to get 500MSPS sample, clock should be 500MHz. But in "7.8 Timing characteristics", it is mentioned that "device clock frequency = 1 GSPS, output sampling rate = 500 MSPS". Please correct me where i am missing the things.
3. As per ADS54J69 Datasheet, "on page no.13, figure 2", for every sample data bits are D11 to D20 for "DA0p & DA0m" and D1 to D10 for "DA1p & DA1m". So total 20 bit is for every sample. But ADC is for 16 bit resolution. Please clarify.
4. Is is ok to connect SYSREF, CLKIN & DxP/DxM to same GTH bank of Xilinx FPGA,or anything should be taken care. (Note:The control interface is connected to HD bank of Xilinx FPGA).
Thanks
