DAC38RF82EVM: DAC38RF82EVM + TSW14J56EVM: locking output data stream (9Gsps) to an external clock source(SMAj4)

Hi,

One of our engineers will look into your question.

If you have questions regarding LMK04828 setup, please address this in the clocking forum. 

Hello,

After reviewing your question again, I believe you may refer to the following app note for detail:

This is a system level planning so it is hard to see where you are going exactly.

Antonio Guardiani said:

My idea was to use a nested 0-delay dual loop to achieve fixed phase relationship between clkin1 (the 80.082 Mhz source of the pulsed laser) and the digital data at 8.84736Gsps converted by the dac.

The above question will need to be addressed by the clocking team in detail also as another part of puzzle. The zero delay loop synchronizes the clocks based on the 80.082MHz  phase frequency detector of the first loop. The 80.082MHz will also need to have some sort of multiplication factor with respect to the DAC clock generation. The problem is that the LMK04828 cannot generate such high speed clock at 8847.36MHz.

You may configure the DAC on-chip PLL with 80.082MHz as the PFD as a starting point for a similar DACCLK to the 8847.36MHz (Not exact due to the multiplication ratio of 80.082MHz not being integer divisible.). You will need to check if any of the integer multiple of 80.082MHz DACCLK will fit your application and generate the appropriate DACCLK that will work in your system. Basically, besides the zero delay loop of the LMK, you will have another loop in the DACCLK PLL stage that generates the high speed DACCLK based on the 80.082MHz.

We cannot configure the LMK04828 setting for you. You will have to plan this out on a system level and ask the clocking team for assistance or use the clocking configuration tool accordingly.