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TPL0401A-10: Timing to read register

Tomoaki Yoshida91
Genius 5255 points
Part Number: TPL0401A-10
Other Parts Discussed in Thread: USB2ANY, TPL0102EVM

Hi Team,

I have a question for timing to read register.

Several methods are specified for register read operations in the datasheet.

<Questions>

#1.

How should the three reading methods below be used properly?

#2.

Is there a time limit to reading the result after writing to the register?

Reading is prohibited immediately after writing, and reading is prohibited when a certain time has elapsed.

Whether there are restrictions such as reading being disabled after a certain time after writing.

I would like to know if there is a register cleanup or update period.

Best regards,

Tomoaki Yoshida

  • 0
    TI__Genius 14220 points

    Hi Yoshida-san,

    Thank you for your query. I don't see any mention of any other timing requirement between a read and a write cycle except tBUF. I think any standard I2C interface should meet this. 

    However, as this is an old part, I think I should check it myself on the EVM. I need a day to acquire and test this on the EVM. I will get back with my findings with you by tomorrow.

    Thanks for your patience.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DAC

  • 0 in reply to Uttam Sahu
    Genius 5255 points

    Hi Uttama-san,

    Thank you for your support.

    How about is the test result on the EVM?

    Could you please let me know if you have any updates on this matter?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 14220 points

    Hi Yoshida-san,

    I couldn't test it on the EVM yet due to the busy schedule in the year-end. I will get back by the end of this week.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    TI__Genius 14220 points

    Hi Yoshida-san,

    I got some time today for testing the I2c read on the TPL0102EVM which is from the same family of DPOTs. I used the USB2ANY controller to perform the read operation. I had to make two packets manually for the read. I saw some issues with the consistency of the read pattern. I couldn't conclude anything at the moment and I will need some more time for analyzing the actual behavior. As this is the year-end, I will be on vacation until the end of the year. I can look into this once I am back but if someone else can find some bandwidth from my team for this you may get a result sooner. However, please expect a slower response due to the holidays.

    Sorry for keeping you waiting so long. I am unable to find an answer from the design team as this is an old part. So, my only option is to provide you a solution by testing it on the hardware.

    Regards,

    Uttam