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DM368 encode 1080i

Other Parts Discussed in Thread: TVP7002

Hi 

We are working on DM368 with encode application (based on the encode example)

 

The encode works fine up to 720P using the TVP7002 . We have modified the encode to support  1080i but than the Capture thread hangs (waits) in 

 

while (!gblGetQuit())
 {
  dprintf("$$2\n");
        /* Pause processing? */
        Pause_test(envp->hPauseProcess);

   dprintf("$$2b\n");

 

        /* Capture a frame */
        if (Capture_get(hCapture, &hCapBuf) < 0) {     // Here it hangs
            ERR("Failed to get capture buffer\n");
            cleanup(THREAD_FAILURE);
        }

once in few second it returns with a valid frame but most of the time it just waits.

The TVP7002 seems to be locked and it status registers indicates correct lines number and Vsync signal is active.

what can cause the capture thread behavior? , is some one implemented 1080i capture with DM368/TVP7002 ?

Any tips here?

Thx

Avi

  • Below are typical TVP7002 1080i60Hz settings used.  You may want to compare these settings to those being used with the DM368 platform.  The input MUX settings may not be set properly for your system. 

    BR,

    Larry

     

    ////////////////////////////////////////////////////////////////////////////////

    BEGIN_DATASET  // Appended by WinVCC4 v4.51.  Saved all registers.

    DATASET_NAME,"TVP7002_1080i - 60Hz - 33.75 Khz - 74.25Mhz, 20bit 422, Embedded Syncs"
    //7000
    WR_REG,TVP7000,0x01,0x01,0x89 // PLL DIVMSB   2200              
    WR_REG,TVP7000,0x01,0x02,0x80 // PLL DIVLSB                 
    WR_REG,TVP7000,0x01,0x03,0x98 // PLL CONTROL                
    WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
    WR_REG,TVP7000,0x01,0x05,0x32 // CLAMP START                
    WR_REG,TVP7000,0x01,0x06,0x20 // CLAMP WIDTH
    WR_REG,TVP7000,0x01,0x07,0x2C // HSYNC OUTPUT WIDTH - 44
    WR_REG,TVP7000,0x01,0x0B,0x80 // Cb ALC blank level = 512h
    WR_REG,TVP7000,0x01,0x0C,0x90 // Y ALC blank level = 40h 
    WR_REG,TVP7000,0x01,0x0D,0x80 // Cr ALC blank level = 512h
    WR_REG,TVP7000,0x01,0x0E,0x3F // SYNC CONTROL    Force SOG, VS/HSout++
    WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x10,0x5D // SOG Threshold-(YPbPr Clamp)   
    WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD   
    WR_REG,TVP7000,0x01,0x12,0x00 // PRE_COAST                  
    WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST                 
    WR_REG,TVP7000,0x01,0x15,0x47 // Output Formatter, bt 601 range, embedded syncs
    WR_REG,TVP7000,0x01,0x16,0x01 // MISC Control 
    WR_REG,TVP7000,0x01,0x17,0x00 // Outputs enabled
    WR_REG,TVP7000,0x01,0x18,0x01 // T-SW disabled, blank off, CSC disabled, FID,SOG,CLK polarity=invert      
    WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT    CH1 selected (BNC )
    WR_REG,TVP7000,0x01,0x1A,0xCF // SOG LPFand CLP LPF, ext  REF CLK, INPUT MUX SELECT  HSYNC_B and VSYNC_B selected
         
    WR_REG,TVP7000,0x01,0x21,0x35 // HSOUT START
    WR_REG,TVP7000,0x01,0x22,0x00 // Macrovision support                
    WR_REG,TVP7000,0x01,0x26,0x80 // ALC Enable      
    WR_REG,TVP7000,0x01,0x28,0x53 // AL FILTER Control          
    WR_REG,TVP7000,0x01,0x2A,0x07 // Enable FINE CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
    WR_REG,TVP7000,0x01,0x2D,0x00 // Coarse Clamp OFF
    WR_REG,TVP7000,0x01,0x2E,0x80 // SOG Clamp ON
    WR_REG,TVP7000,0x01,0x31,0x5A // ALC PLACEMENT

    WR_REG,TVP7000,0x01,0x34,0x13 // Macrovision Stripper Width use 13h if EXT 27M REFCLK is used
    //WR_REG,TVP7000,0x01,0x34,0x07 // Macrovision Stripper Width use 07h if internal REFCLK is used

    WR_REG,TVP7000,0x01,0x3F,0x0F // Input B/W

    //embedded syncs
    WR_REG,TVP7000,0x01,0x40,0x07 // AVID Start  263 (236+27)  for SOG filter differnence
    WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start
    WR_REG,TVP7000,0x01,0x42,0x8B // AVID Stop  2187 (AVID start + 1920 + 4)
    WR_REG,TVP7000,0x01,0x43,0x08 // AVID Stop

    WR_REG,TVP7000,0x01,0x44,0x02 // VBLK F0 Offset
    WR_REG,TVP7000,0x01,0x45,0x02 // VBLK F1 Offset
    WR_REG,TVP7000,0x01,0x46,0x16 // VBLK F0 Duration
    WR_REG,TVP7000,0x01,0x47,0x17 // VBLK F1 Duration
    WR_REG,TVP7000,0x01,0x48,0x00 // F-bit
    WR_REG,TVP7000,0x01,0x49,0x00 // F-bit


    END_DATASET