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DAC38J84: Does LMK04828 Dynamic Digital Delay Necessarily Break the DAC38J84 Input JESD Link?

Todd Rockoff
Intellectual 480 points
Part Number: DAC38J84
Other Parts Discussed in Thread: LMK04828,

Dear Helpers, 

We are developing a system wherein DAC38J84 receives DACCLK from LMK04828 DCLKout2.

The DAC PLL is bypassed in DAC38J84, such that the DACCLK pins provide the SerDes PLL reference input directly.

Now that everything is working fine from power up, we would like to adjust the phase of DACCLK on the fly by applying LMK04828 dynamic digital delay to DCLKout2.

Unfortunately, delaying or advancing DCLKout2 by a single VCO cycle causes the DAC38J84 JESD RX FSM to assert SYNCb.

I suspect that the JESD link breaks for this reason: The SerDes PLL momentarily loses lock when the DACCLK interval is abruptly stretched or shortened for one cycle, therefore the JESD RX FSM resets, therefore the JESD link needs to be re-established.

Q1) would you kindly confirm my understanding of the phenomenon that we are observing?

Q2) I'm wondering whether we could harness the DAC PLL to allow on-the-fly DACCLK phase adjustment without breaking the JESD link?

Hopeful thanks --todd

  • 0
    TI__Genius 12780 points

    Hi Todd,

    One of our device experts will be back with you soon.

    Best Regards,

    Dan

  • 0
    TI__Guru* 91947 points

    Todd,

    This appears to be the case. How much delay are you applying? Are you also applying this delay to the FPGA reference clock as well? Is the DAC SYSREF input disabled when you apply this delay? Could you not use the DAC digital phase delay to accomplish what you need?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 480 points

    Thank you for following up promptly, Jim.

    > How much delay are you applying?

    TR: DIV = 20 for all DCLKoutX. dacclk_ddly is the delay of DCLKout2 relative to all the other DCLKoutX outputs. Operator specifies dacclk_ddly via Nios console in the range from -40 to +40 VCO half cycles.To change dacclk_ddly, Nios sets the HS (half-step) appropriately. To increase dacclk_ddly, set CNTH/CNTL = 10/11, and to decrease dacclk_ddly, set CNTH/CNTL = 10/9. Then the SW writes DDLYd_STEP_CNT accordingly.

    > Are you also applying this delay to the FPGA reference clock as well?

    TR: No, all of the other clock phases remain at offset 0. The purpose of varying the DACCLK phase is only to change the phase of the sampling instant w.r.t. the ADC sampling instant in the system.

    > Is the DAC SYSREF input disabled when you apply this delay?

    TR:No, 0x5C is programmed to 0x1111. I notice also that the LMK's SDCLKoutX outputs are not individually disabled. Is it possible that the SYNC event controlling the single-cycle substitution of the divide counts also generates a SYSREF pulse? I could instead program 

    > Could you not use the DAC digital phase delay to accomplish what you need?

    TR: We were planning to use the fractional FIR filter delays in addition to changing the phase of the DACCLK. The per-channel FIR delays will be most important for our application. It should be possible to apply both kinds of phase adjustment to the conversion, yes?

    Hopeful thanks --todd