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ADC12DJ3200: keeping the ADC in power down at Power Up

LALIT VERMA
Expert 1695 points
Part Number: ADC12DJ3200

Hi,

I want to keep ADC12DJ3200 in power down mode by default at power up by pulling up the PD pin high.

PD pin will be connected to FPGA and then FPGA will make the PD pin low when it wants the data from ADC.

But in datasheet it is written that power down using PD should not be used for long time.

So can we use PD pin for power down ADC at power up or is there any other method to keep ADC in power down or in reset mode?

Actually we will be using a custom GUI for our project and we want data from ADC to FPGA only when user selects the option in GUI.

So is there any method other than using PD, to stop ADC from sending digital data to FPGA?

An early response will be highly appreciated.

Thanks,

Lalit  

  • 0
    TI__Genius 12780 points

    Hi Lalit,

    We are taking a look into your question, and will be back with you as soon as possible.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    TI__Mastermind 38690 points

    Hi Lalit,

    I apologize for the delay.

    There are really only a couple of options here, since the PD pin cannot be used this way as specified in the datasheet.

    1) apply power to the ADC and quickly apply a power down via the appropriate spi writes, the downside is that board will experience a bump in power for a short period of time.

    2) my other recommendation, which I have used before, is to put a load switch in series with each ADC supply. This way you can independently control all of the power supplies to the adc. This will keep the power down, until the load switch is written to by the FPGA, etc.

    www.ti.com/.../overview.html

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Expert 1695 points

    Hi Rob,

    Thanks for the suggestions.

    But I have some more queries about "PD" pin for you: 

    Is the recommendation of not using "PD" pin for power down is for the case when ADC is already configured and running and then suddenly "PD" pin is made high to put ADC in power down.

    OR 

    Is it also recommended to not use "PD" for power down even when ADC is only power up but not configure through SPI?

    I am assuming recommendation to not use "PD" is for the case when ADC is already configured and doing the conversion. So one should not power down ADC when it is converting the Analog Signal into Digital and sending the digital data to FPGA using SERDES because performance of SERDES may degrade.

    But let's say if ADC is not configured and only voltage is applied to ADC power supply pins then can I keep ADC in power down using "PD" pin?

    Then after taking out ADC from power down mode, will configure the ADC using SPI and then will not use the "PD" pin to put ADC in power down until next power cycle.

    Can I use "PD" pin for the case I have mentioned above?

    An early response will be highly appreciated.

    Thanks,

    Lalit

  • 0 in reply to LALIT VERMA
    TI__Mastermind 38690 points

    Hi Lalit,

    The case you have described above won't work unfortunately.

    It is really recommended that the supplies be disconnected to save power as described in the datasheet rather than use the PD or Mode settings.

    Regards,

    Rob