Hi Team,
One of our customer using DAC5682Z high speed DAC.
They are interfacing FPGA to DAC5682Z, The application is to make the DAC work at 1GSPS. The FPGA also configures DAC configuration registers via 4wire serial interface.
They want to use DAC'S internal PLL for locking on to DAC's reference clock which is about 500MHZ and multiply this reference frequency with the ratio defined by configuration register "9",also by VCO DIV/2 bit in configuration register "11",PLL_gain and range settings to 1GSPS and 480MSPS on page 11 of the data sheet into configuration register "11" and even a PLL_LPF_RESTART in the same register.
Please provide register settings to lock PLL/DLL.
Thanks & Best Regards,
Amit Mane
