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ADS131E08: Dithering

Carl Moreland
Prodigy 30 points

Part Number: ADS131E08

I'm using the ADS131 in an application where it is highly preferable to synchronize the ADC to a demodulated signal, and whereby the demodulation itself is synchronized to the AC mains (60Hz). I'm using a digital PLL to sync the ADS131 to 900Hz (60Hz*15) and I maintain frequency & phase lock by dithering the 2MHz clock. My question is, will clock dithering affect SNR? The signal bandwidth is only 10 Hz so I'm not concerned with jitter-induced noise, but I don't know how clock stability affects the internal conversion mechanics.

  • 0
    TI__Guru** 100925 points

    Carl,


    I'm not entirely sure that I understand all of your system. However, it looks like you're asking about the effects of having a master clock that has some variance to adjust to the demodulated signal that is synchronized to 900Hz.

    First, I don't know of any characterization data of the device to look at that type of variance in the master clock. It's not something that we normally characterize. We may look at the effect of jitter on the device, but in many cases, the input clock is divided by two as it enters the digital. This reduces the problem of jitter. I'm not sure if the ADS131E08 is one of these devices, but the modulator rate is the input clock divided by 2 and specifications of latching in . Note that I haven't found any data on jitter for this device.

    For most delta-sigma devices, the data is likely tolerant to small changes in the master clock. Data is sampled at a lower rate (modulator rate) and then the data output at an even lower rate. In the ADC, the input voltage is sampled onto an input sampling capacitor and any error from sample to sample would show an error or noise. It depends on your system, but if theres a variation in the input clock of only 1% or so, there won't be much difference in the sampled value.

    Also, if you're using some sort of PLL, I would imagine that the clock frequency would be rather stable, with only small, slow changes to the clock frequency. If that's the case, the device wouldn't show much change in operation or any variation in sampling.

    My guess is that you would see very little, if any change in SNR. However, I haven't seen any kind of characterization on this.



    Joseph Wu