ADS54J60: ADS54J60 end to end latency calculation

Gary Beck

Part Number: ADS54J60

I have a design using an ADS54J60 and Xilinx Kintex UltraScale FPGA. Need to determine the end to end latency.

I understand the latency from the sample to the serial output is 134 clocks + 4ns (refer to ADS54J60 datasheet figure 2). This parameter also appears to be tLAT-ADC as seen in TIDU171 figure 3.

Would seem that to be able to calculate the end to end latency the parameter tTX-LMFC needs to be known.

Has anyone else performed this calculation?

Any help would be appreciated.

Thanks, Gary

over 6 years ago

0 dBrock over 6 years ago

TI__Genius 12780 points

Hi Gary,

We are taking a look into your question, and will be back with you soon.

Best Regards,

Dan

0 jim s over 6 years ago

TI__Guru* 91947 points

Gary,

See if these numbers help you:

t_{TX_LMFC} = 24 clocks of ADC_CLK

t_{TX_SER} = 32 clocks of ADC_CLK

t_{TX_IN} = 102 clocks of ADC_CLK (where 134 is the total latency from Analog input to JESD serializer output)

Regards,

Jim

0 Gary Beck over 6 years ago in reply to jim s

Prodigy 190 points

Jim,

Thanks for the quick reply! These are exactly the numbers needed.

Just to verify... tTX_IN is the same parameter as tLAT-ADC as shown in TIDU171 Figure3.

Regards, Gary

0 jim s over 6 years ago in reply to Gary Beck

TI__Guru* 91947 points

Gary,

I think so but not 100% sure. The engineer who did that document is no longer with TI, so I could not confirm. The answers I provided did come from the IC designer.

Regards,

Jim

Data converters

Data converters forum

ADS54J60: ADS54J60 end to end latency calculation