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ADS7953: throughput rate versus source impedance

Hans van de Laar
Prodigy 130 points
Part Number: ADS7953

Hi,

I would like to have some verification:

In the datasheet revision SLAS605C, chapter 9.2 typical applications.

Several graphs are given for the throughput rate versus Source resistance.

How is the throughput rate lowered during these tests? By lowering the clock frequency? And/or extending the acquisition phase?

I assume in the unbuffered situation, the acquisition time is the main contributor.

But in the buffered MXO, the analog IP settling becomes the main contributor.

Is my assumption correct?

In our case we have an throughput rate of 80ksps. But with a 20MHz clock during settling time and 325ns acquisition time.

According to the datasheet graphs you can go to 10kOhm, but think (almost know for sure) that is not valid in our case.

Regards, Hans

 

  • 0
    TI__Mastermind 25020 points

    Hello,

    The sampling rate was likely decreased by decreasing the clock rate, which naturally elongates the acquisition time.

    In the unbuffered situation, the .

    With the buffer, the ADC no longer deals with this as the buffer addresses it.

    Each case scenario will differ though as you point based on the use case. If you are not using the buffer, I would suggest confirming that the ADC is settling when two subsequent channels when set 95% of the full scale range apart. If not, you will need to modify your charge bucket filter (the input RC values) if the sample rate cannot change.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Prodigy 130 points

    Hi Cynthia,

    Thanks for your quick reply.

    "The sampling rate was likely decreased by decreasing the clock rate, which naturally elongates the acquisition time" --> I understand, but it would be nice to have the test conditions verified.

    "In the unbuffered situation, the ." --> line not finished.

    I have a buffer in place in and will verify the behavior.

    Regards, Hans

  • 0 in reply to Hans van de Laar
    TI__Mastermind 25020 points

    Hello,

    With the holidays, getting this information will be timely. I am quite certain that it is through decreasing the clock rate.

    Apologies, in the unbuffered situation, the input can be at each end of the analog input range, say GND, and Max. when the mux changes between these levels at the channels, and the ADC is exposed to this drastic voltage step, will affect linearity and THD as the input settling time will be longer

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Prodigy 130 points

    Hi Cynthia,

    About the clockrate: for me its clear now. But it would be nice if this information is added to the datasheet.

    About the unbufferd situation; clear.

    Thanks for your assistance.

    Regards, Hans